Kotb Jabeur

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications. A case study of this nonvolatile flip-flop is considered. In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation. We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ. Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell. At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ.

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Compact Modeling of a Magnetic Tunnel Junction Based on Spin Orbit Torque

High endurance, high speed, scalability, low voltage, and CMOS-compatibility are the ideal attributes of memories that any integrated circuit designer dreams about. Adding non-volatility to all these features makes the magnetic tunnel junctions (MTJs) an ultimate candidate to efficiently build a hybrid MTJ/CMOS technology. Two-terminal MTJs based on spin-transfer torque (STT) switching have been intensively investigated in literature with a variety of model proposals. Despite the attractive potential of the STT devices, the issue of the common writing/reading path decreases their reliability dramatically. A three-terminal MTJ based on the spin-orbit torque (SOT) approach represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing paths. In this paper, we introduce the first compact model, which describes the SOT-MTJ device based on recently fabricated samples. The model has been developed in Verilog-A language, implemented on Cadence Virtuoso platform and validated with Spectre simulator. For optimized simulation accuracy, many experimental parameters are included in this model. Simulations prove the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits. Innovative logic circuits based on the SOT-MTJ device, modeled in this paper, are already in progress.

Compact model of a three-terminal MRAM device based on Spin Orbit Torque switching

The combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward an universal memory. Although an expanding attention is given to two-terminal Magnetic Tunnel Junctions (MTJ) based on Spin-Transfer Torque (STT) switching as the potential candidate for future memories, its reliability is significantly decreased because of the common writing/reading path. Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ultimate MRAM. It represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing path. This paper represents simulation results of the first compact model which describes the SOT-MTJ device based on recently fabricated samples. The model is developed in Verilog-A language, implemented on industrial CAD platform and validated by electrical simulations. Many experimental parameters are included in the model in order to enhance simulation accuracy. Based on simulations results, we show the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits.

Beyond STT-MRAM, Spin Orbit Torque RAM SOT-MRAM for High Speed and High Reliability Applications

For 40 years, microelectronics has been following the Moore’s law, stating that the density and speed of integrated circuits would double every 18 months. However, this trend is presently getting out of breath, because of incoming insurmountable physical limits. Due to decreasing devices size, leakage current is becoming the main contributor to power dissipation of CMOS. Furthermore, the increased density and reduction in die size lead to heat dissipation and reliability issues. Moreover, the dynamic power keeps on growing up with both clock frequency and global capacitance while the power supply is not scaled down accordingly. Several solutions are investigated to try to push forward these limits at technology, circuit or architecture levels. The “more than Moore” concept consists in using new devices beside or in replacement of standard CMOS transistors. For instance, the use of non-volatile devices is seen as a promising solution to reduce power consumption, improve reliability and offer new functionalities. Several technologies are intensively investigated like Phase Change Random Access Memory (PCRAM), Ferroelectric RAM (FeRAM), RedoxRAM (ReRAM) and Magnetic RAM (MRAM). In its 2010 report, ITRS identified RedoxRAM and STT-MRAM as the two most promising technologies for embedded memories at technology nodes below 16 nm. The combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward a universal memory. Although an expanding attention is given to two-terminal Magnetic Tunnel Junctions (MTJ) with writing based on Spin-Transfer Torque (STT) switching as the potential candidate for future memories, it suffers from weaknesses. Indeed, two main shortcomings are still limiting the reliability and endurance of STT-MRAMs: i) The high current density required for writing can occasionally damage the MTJ barrier, specially for switching on the nanosecond time scale ii) It remains a challenge to fulfill a reliable reading without ever causing switching for very advanced technology nodes, since writing and reading operations share the same path, through the junction. Indeed, the smaller the MTJ the lower the writing current without having the possibility to reduce the reading current to maintain a reliable sensing. Three-terminal MTJ with writing based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ultimate RAM. It represents a pioneering way to triumph over current two-terminal MTJ’s limitations by separating the reading and the writing paths, completely avoiding tunnel barrier damaging and read disturb issues.

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories

The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.

Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures

This paper gives an overview of hybrid CMOS/magnetic logic circuit design. We describe the magnetic devices, the expected advantages of using them beside CMOS to help to circumvent the incoming limits of VLSI circuits and the tools required to design such circuits, including Process Design Kit (PDK) and Standard Cells (SC). As a case of study, we particularly focus on a new and promising device technology based on Spin Orbit Torque (SOT) effect.

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting processing performances. One of the solutions is to rely on NonVolatile Memories (NVM) and their integration within complex computing systems, but the association of heterogeneous technologies remains a real challenge. In this paper, we describe a fully embedded System-on-Chip (SoC), i.e., without external memory interface. We discuss the benefits of embedding NVM elements into the system in terms of power consumption and functionality enhancements compared to an equivalent system relying on standard volatile memory blocks. We depict the complete design from the block-diagram down to the layout of the fully functional non-volatile SoC. Our methodology includes the conception of a single bit memory cell up to the benchmarking of the architecture, in a hybrid magnetic/CMOS low-power technology, regarding the industrial constraints past experimentation in the aim to reach the quality of commercial products. We present precise pre-silicon performance estimations, using different configurations of compression algorithms as reference benchmarks that show where energy is mainly consumed.

Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC

This paper describes the design and the evaluation of a low-power System-on-Chip (SoC) in an advanced hybrid 40nm magnetic/CMOS technology node. Without external memory interface, the processor of the SoC benefits from a privileged access to the embedded NVM (Non-Volatile Memory), providing means for internal data storage and integrity thanks to its inherent non-volatility. Furthermore, a method based on an IRQ (Interrupt Request) controls the instant-on/off features of the SoC at assembler level through the use of NVM elements and improves the whole system in terms of power consumption and functionality enhancements, compared to an equivalent system relying on standard volatile memory blocks only. We discuss our simulation results on the basis of still image compression benchmarks at various data throughputs and show the benefits of NVM even for rather computation intensive algorithms.

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack

To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors (“Sensing”), RF receivers (“Communicating”) and logic/memory (“Processing/Storing”) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC) as the enabling technology platform for Internet of Things (IoT). This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). The major outputs of GREAT are the technology and the architecture platform for IoT SoCs providing better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT-MTJs (now viewed as the most suitable technology for digital applications and with a huge potential for analog subsystems) unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way since the MSS will enable different functions using the same technology.