Rajendra Bishnoi

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as nonvolatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this paper, we provide a very detailed analysis of SOT-MRAM at both the circuit-and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybrid-combination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60% while the performance increases by 1% compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is 27× smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65 nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.

Avoiding unnecessary write operations in STT-MRAM for low power implementation

Spin Transfer Torque (STT) is a promising emerging memory technology because of its various advantages such as non-volatility, high density, virtually infinite endurance, scalability and CMOS compatibility. Despite all these features, high write current is still a challenge for its widespread use. When writing a value that is already stored, a significant current flows through the Magnetic Tunnel Junction (MTJ) cell which is almost the same as that required to flip the stored data. This increases the total power consumption of the memory. To address this issue, we propose a technique which can avoid unnecessary write operations with bit-level granularity. Our technique can save 68.9% of the total write power consumption with a minor area overhead (0.68 %) and only a small timing penalty (1.33 %).

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Architectural aspects in design and analysis of SOT-based memories

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as non-volatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that with a hybrid-combination of SRAM for the L1-cache and SOT-MRAM for the L2-cache the energy consumption can be reduced by 63 % in average while the performance can be increased by 1 %. In addition, the memory area is 43% lower compared to an SRAM-only configuration.

Read disturb fault detection in STT-MRAM

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has potential to become a universal memory technology because of its various advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read disturb is a major reliability issue in which a read operation can lead to a bitflip, because read and write current share the same path. This major reliability challenge is growing with technology scaling as read to write current ratio decreases. In this paper, we propose a circuit-level technique to detect read disturb by sensing the current during the read operation. Experimental results show that the proposed technique can effectively detect read disturb at the cost of negligible power and area overhead.

Layout-Based Modeling and Mitigation of Multiple Event Transients

Radiation-induced multiple event transients (METs) are expected to become more frequent than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a fast and accurate layout-based soft error rate (SER) assessment technique with consideration of both SET and MET fault models is presented. Despite existing techniques in which the adjacent MET sites are extracted from a logic-level netlist, we conduct a comprehensive layout analysis to obtain MET adjacent cells. Experimental results reveal that the layout-based technique is the only viable solution for identification of the adjacent cells as netlist-based techniques considerably underestimate the overall SER. Furthermore, by identifying the most vulnerable adjacent cells and increasing their physical distance in the layout using local adjustment rules, we are able to considerably reduce the overall SER without imposing any area and performance penalty.

Self-Timed Read and Write Operations in STT-MRAM

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising memory technology because of its advantageous features, such as nonvolatility, scalability, high density, zero-leakage, and CMOS compatibility. However, one of its major drawbacks is the high overall energy consumption. To make matters even worse, the write process in STT-MRAM is of stochastic nature, i.e., the completion of a write operation is nondeterministic. However, if the read/write completion could be detected on the fly (i.e., dynamically) and the respective components could be turned-OFF immediately, the energy consumption can be reduced by a large extent. Therefore, we propose a technique where the read and write completion signals are generated asynchronously on the fly using a self-timed bitwise technique. With this approach, the memory consumes power only when it is in the actual operational mode. Experimental results show that this technique significantly reduces the energy consumption of read and write operations with negligible area overhead.

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing

With technology scaling, conventional CMOS-based flip-flops can no longer efficiently cope with the increasing leakage power challenge. Therefore, various non-volatile flip-flop designs were recently introduced to reduce the static power consumption. However, these flipflop architectures employ non-volatile Magnetic Tunnel Junction (MTJ) storing devices only for backup, i.e. to save and restore the content before and after power gating. This limits their efficiency for aggressive power gating for effective power reduction. To overcome this limitation, we propose a novel Non-Volatile Non-Shadow flip-flop (NVNS-FF) using Spin Orbit Torque (SOT) based MTJ cells. In this design, we exploit the high speed, low energy and high-reliability features of SOT devices to employ them as active components of the flip-flop. This enables efficient normally-off computing by allowing very aggressive power gating for both short and long standby periods. Experimental results show that the NVNS-FF has similar energy and timing characteristics as conventional CMOS-based flip-flops in active mode, and at the same time it allows to reduce the static power by 5X compared to backup flip-flops.

Improving Write Performance for STT-MRAM

Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average.

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices

Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.