Clara Isabel Lujan-Martinez

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor alpha les 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of alpha on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of alpha (alpha = 0, 0.5, and 1) in a 0.5 mum CMOS technology with plusmn1.65-V supply voltage. Experimental results show (for alpha = 1 ) a THD of - 57 dB (HD2=-70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 muA/V and a power consumption of 3.2 mW.

A Tunable Pseudo-Differential OTA With

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-mum CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-Vpp input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption.

-78~{\hbox {dB}}

Digital video broadcasting terrestrial (DVB-T) is being adopted by many countries all over the world. Recently, DVB-H, a new standard compatible with DVB-T, has been proposed for handheld terminals, which demands low power consumption. In this study, a continuous-time filter for DVB-T/H receivers is presented. High linearity and low noise are achieved by selecting a Gm-C filter topology implemented with a novel programmable transconductor based on MOS transistors in the triode region. The filter is tunable in a wide range, which makes it suitable for VLSI integration. The filter has been designed in a standard 0.5 m CMOS technology with a single 3.3 V supply voltage. Experimental results show an IM3 of 58 dB for a two tone experiment with 2 Vpp output signal centred at 2 MHz.

THD Consuming 1.25 mW

Programmable linear resistors are usually implemented using MOS transistors biased in the triode region. Recently a technique, based on quasi-floating-gate transistors, has been introduced to linearize the V-I characteristic of a MOS transistor operating in the ohmic region. In this paper an improved programmable linear resistor also based on quasi-floating gate techniques is presented, which provides a larger conductance than the conventional fixed gate- voltage implementation and features better performance in terms of linearity.

Low-power baseband filter for zero-intermediate frequency digital video broadcasting terrestrial/handheld receivers

This paper proposes a novel very linear tunable transconductor based on local feedback loops. The linear V-I conversion is accomplished using MOS resistors based on quasi-floating gate transistors. The absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and decrease of nonlinear distortion. The OTA was designed in a 0.5 mum CMOS technology with plusmn1.65-V supply voltage. Simulation results show a THD of -80 dB at 100 kHz with 1 Vpp input signal. Good linearity of the OTA over a large tuning range is obtained.

Comparison of programmable linear resistors based on quasi-floating gate MOSFETs

A novel CMOS highly linear tunable pseudo-differential transconductor is presented. By using different linearization techniques, a new fully CMOS OTA has been designed that outperforms previous CMOS pseudo differential OTA implementations in terms of linearity. It has been designed in a 0.5 mum-CMOS technology with a single 3.3 V voltage supply. Experimental results show a IM3 of -72 dB for a 1 Vpp input signal at 2 MHz with a current consumption under 5 mA. A large tuning range is obtained with the IM3 always under -70 dB for the same input signal.

A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor

This paper presents a new tunable pseudo-differential transconductor topology. A compact feedback loop able to operate with low supply voltage is employed that holds the input transistors in triode region and provides high output resistance. This control loop allows keeping high linearity in a wide range of transconductance. The circuit has been fabricated in a 0.5 μm CMOS technology with a power supply of 1.8 V. The transconductance gain is tunable from 15 to 165 μA/V with a measured total harmonic distortion of −67 dB at 1 MHz for an input voltage of 1 Vpp. The circuit maintains the linearity at higher frequencies with a third-order intermodulation below −55 dB at 10 MHz.

A −72 dB @ 2 MHz IM3 CMOS tunable pseudo-differential transconductor

A novel CMOS linear transconductor is presented. It is basically an improvement of the classical telescopic cascode OTA with source degeneration in which the resistor has been implemented using quasi-floating-gates transistors. It also allows compact implementation of common mode voltage control circuitry in order to save area and power consumption. This transconductor has been designed in a 0.5 mum CMOS technology and the results obtained show a THD of -61 dB at 10 Mhz for a 1 Vpp output voltage. In order to show the feasibility for the implementation of tunable Gm-C filters using the proposed transconductor, a 1 MHz tunable third order Chebyshev low-pass filter suitable for Bluetooth applications has been experimentally validated.

A low-voltage, high linear programmable triode transconductor

In this paper different parts of a wake-up receiver for wireless sensor node are presented. The circuit is composed of an amplifier with input impedance matching network and an envelope detector both working at 868 MHz. The amplifier is incorporated in order to increase the sensitivity of the wake-up receiver. The amplified signal passes to the envelope detector which demodulate on-off keying signal at 125 kHz. The circuits have been designed to optimize power consumption and area. The total power consumption and the minimum signal detected are 44.32 uW and 0.4 mVp respectively. The circuits were implemented in UMC CMOS 65 nm process.

A CMOS linear tunable transconductor for continuous-time tunable Gm-C filters

This paper presents the design of a low power temperature sensor based on temperature-to-frequency conversion for RFID applications. The variation of temperature is detected by a PTC resistor that determines the reference current of a bootstrapped cascode source. This current is used to bias an active inductor. The self-resonance frequency varies accordingly to the shift of the current, thus providing the temperature to frequency conversion. The circuit has been implemented using a standard 65 nm CMOS technology. A frequency of oscillation of 31.3 MHz at 20°C has been obtained, with an estimated sensitivity of 50.5 kHz/°C, a resolution of 0.12°C and a power consumption of 21.8 uW within the 0-80°C temperature range.