Guillermo Indalecio

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

The fin-edge roughness (FER) and the TiN metal grain work function (MGW)-induced variability affecting OFF and ON device characteristics are studied and compared between a 10.4-nm gate length In0.53Ga0.47As FinFET and a 10.7-nm gate length Si FinFET. We have analyzed the impact of variability by assessing five figures of merit (threshold voltage, subthreshold slope, OFF-current, drain-induced-barrier-lowering, and ON-current) using the two state-of-the-art in-house-build 3-D simulation tools based on the finite-element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the subthreshold region while, in the ON-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In0.53Ga0.47As FinFET is more resilient to the FER and MGW variability in the subthreshold compared with the Si FinFET due to a stronger quantum carrier confinement present in the In0.53Ga0.47As channel. However, the ON-current variability is between 1.1 and 2.2 times larger for the In0.53Ga0.47As FinFET than for the Si counterpart, respectively.

Statistical study of the influence of LER and MGG in SOI MOSFET

A 3D drift-diffusion device simulation tool with quantum corrections has been applied to study the off-current, threshold voltage and sub-threshold slope variability induced by the metal gate granularity using a Voronoi approach, and line edge roughness using Fourier synthesis, in a 25?nm Si FinFET. The discretization based on the finite element method allows for an accurate description of the 3D geometry. We have simulated 4000 variations of the device to study the metal gate granularity using four different metal grain sizes. The results for the threshold voltage variability ranged from 8.6?mV, for a 3?nm grain size, to 25.9?mV, for a 10?nm grain size. The effect of the grain size was studied and we found an inverse square root dependence of the variability for the three figures of merit. The mean threshold voltage and sub-threshold slope have monotonous decrease with the decrease in metal grain size suggesting that the device power consumption and switching speed can be improved by reducing the grain size. The corresponding threshold voltage variability can reach up to 8.2?mV when RMS = 3?nm and the correlation length is 50?nm.

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In 0.53 Ga 0.47 As GAA MOSFET

We investigate the impacts of random dopant (RD) and gate workfunction variability on the subthreshold characteristics of a 50-nm-gate-length inversion-mode gate-all-around In0.53Ga0.47As MOSFET using a 3-D finite-element quantum-corrected drift-diffusion device simulator calibrated to experimental data. We have studied threshold voltage, off-current, and subthreshold slope variations. The workfunction variations on the subthreshold characteristics dominate and decrease with the reduction in grain diameter. The simulated grain diameters of 10, 7, and 5 nm exhibit threshold voltage standard deviations of 52, 41, and 27 mV, respectively. These values are larger than those observed in TiN-metal-gate Si FinFETs for a similar gate length. The impact of RD fluctuations is negligible when compared with bulk Si MOSFETs, giving a threshold voltage spread of only 6 mV.

Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions

We have demonstrated, via validation to experimental data for TiN and Ru, that the grains that appear in the metal gate-stacks of nanoscale CMOS devices can be characterized via a two-parameter Gamma distribution (p -values 0.17 and 0.42 for TiN and Ru). Conversely, a previously presented fit that used Rayleigh distribution does not reproduce the experimental data (p -values 3 × 10-14 and 0.0029 for TiN and Ru). Poisson Voronoi diagrams (PVDs) are shown as a suitable algorithm to generate grains with Gamma distribution, via fitting of the distribution of 10 000 grains. We have also compared the PVD variability against the Rayleigh model for both TiN and TaN metal gates, and concluded that Rayleigh approach overestimates the device variability (by 11.9% for the TiN and by 7.14% for the TaN).

Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.

Implementation of numerical methods for nanoscaled semiconductor device simulation using OpenCL

The present work implements solvers with OpenCL of the FGMRES and preconditioned BCGSTAB algorithms. These solvers are integrated in a 3-D simulation tool of nanoscaled MOSFET transistors. Simulations are launched in two different platform devices: NVIDIA Tesla S2050 and Intel Xeon Phi 3120A. The resulting times of execution are compared against the optimized PSPARSLIB version of the FGMRES solver. The results showed that a large computational charge compensate the overhead due to the data transfer time.

Scaling of metal gate workfunction variability in nanometer SOI-FinFETs

A work function variability caused by the metal gate is studied in a 10.7 nm gate length SOI-FinFET in the sub-threshold region at low drain bias using 3D quantum corrected finite element (FE) drift-diffusion (DD) simulations. The variability is compared with that observed in a 25 nm gate length SOI-FinFET. The 3D DD simulations are meticulously calibrated against 3D FE ensemble Monte Carlo simulations with Schrödinger equation based quantum corrections. The calibration adjusted the material parameters that define the mobility model and the density gradient corrections. For the 10.7 nm gate length device, σ(Vth) ranges between 17.8 mV, when the grain size is 10 nm, to 52.2 mV, when the grain size is 3 nm. The SS is less sensitive to variations in the metal grain size (10 nm-3 nm) than in the corresponding 25 nm gate length device. We have also found that the 10.7 nm device shows similarities with a bimodal distribution for both threshold voltage and off current when the grain size is 10 nm due to a large size of the grains compared to the gate.

Study of statistical variability in nanoscale transistors introduced by LER, RDF and MGG

A 3D drift-diffusion device simulator with implemented density-gradient quantum corrections is developed to run hundreds of simulations to gather variability characteristics in non-planar transistors. We have included the line edge roughness (LER), random dopants (RD), and metal gate granularity (MGG) induced variabilities, which are considered to be the most important sources of variability in device characteristics. The simulator is then applied to study a threshold voltage variability in a 25 nm gate length Si SOI FinFET due to LER and MGG. We found that the LER induced threshold variability has a mean value of 344.5 mV and σ of 4.7 mV while the MGG induced has a mean value of 349.9 mV and σ of 13.3 mV an order of magnitude greater than the LER variability.

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

General Workload Manager: A task manager as a service

During the recent past, the demand on High Throughput Computing has been increasing because of the new scientific challenges. Since the access to several computational resources to manage thousands of simulations can be difficult for scientists, different initiatives have tried to provide the scientific community with interfaces that are user-friendly for several computational resources. Usually, these are designed for some specific codes and for a given research field, such as oceanographic, climate modeling and physics, among others. To overcome this situation, we have developed the General Workload Manager (GWM), a universal-purpose very light management system, capable of working with different computing resources with the least configuration as possible, such as HPC and HTC clusters, standalone worker nodes, hypervisor-enabled servers, and cloud platforms. The suggested system is able to deploy thousands of different simulation tasks using several computing resources, and collecting the results in an easy way.