Paul W. Marshall

Review of displacement damage effects in silicon devices

This paper provides a historical review of the literature on the effects of radiation-induced displacement damage in semiconductor materials and devices. Emphasis is placed on effects in technologically important bulk silicon and silicon devices. The primary goals are to provide a guide to displacement damage literature, to offer critical comments regarding that literature in an attempt to identify key findings, to describe how the understanding of displacement damage mechanisms and effects has evolved, and to note current trends. Selected tutorial elements are included as an aid to presenting the review information more clearly and to provide a frame of reference for the terminology used. The primary approach employed is to present information qualitatively while leaving quantitative details to the cited references. A bibliography of key displacement-damage information sources is also provided.

Correlation of Particle-Induced Displacement Damage in Silicon

Correlation is made between the effects of displacement damage caused in several types of silicon bipolar transistors by protons, deuterons, helium ions, and by 1 MeV equivalent neutrons. These measurements are compared to calculations of the nonionizing energy deposition in silicon as a function of particle type and energy. Measurements were made of displacement damage factors for 2N2222A and 2N2907A switching transistors, and for 2N3055, 2N6678, and 2N6547 power transistors, as a function of collector current using 3.7 - 175 MeV protons, 4.3 - 37 MeV deuterons, and 16.8 - 65 MeV helium ions. Long term ionization effects on the value of the displacement damage factors were taken into account. In calculating the energy dependence of the nonionizing energy deposition, Rutherford, nuclear elastic, and nuclear inelastic interactions, and Lindhard energy partition were considered. The main conclusions of the work are as follows: 1) The ratio of the displacement damage factors for a given charged particle to the 1 MeV equivalent neutron damage factor, as a function of energy, falls on a common curve which is independent of collector current. 2) Deuterons of a given energy are about twice as damaging as protons and helium ions are about eighteen times as damaging as protons.

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

Single event effects in circuit-hardened SiGe HBT logic at gigabit per second data rates

This attempt at circuit level single event effects (SEE) hardening of SiGe HBT logic provides the first reported indication of the level of sensitivity in this important technology, Characterization over data rate up to 3 Gbps and over a broad range of heavy ion LETs provides important clues to upset mechanisms and implications for upset rate predictions. We augment ion test data with pulsed laser SEE testing to indicate the sensitive targets within the circuit and to provide insights into the upset mechanism(s),.

Displacement damage in GaAs structures

High-energy knock-on atoms produced by incident protons are much more important in determining the total nonionizing energy deposited in GaAs than in Si, due to the relative size of the Lindhard correction for partitioning the recoil energy. High-energy recoils are mainly produced by inelastic nuclear interactions between the incident protons and the target atoms. A review of previous calculations indicates that both the fast cascade and the evaporation phases of the elastic interaction contribute to the average energy of the recoiling ion. New calculations are presented for the energy dependence of the nonionizing energy deposited in GaAs as a result of inelastic interaction with protons over the energy range 10-1000 MeV. These calculations are combined with the previously determined contribution from elastic interactions to obtain the energy dependence of the total nonionizing energy deposited in GaAs by protons. The calculation is compared with both new and earlier experimental data for ion-implanted GaAs resistors irradiated with protons over the energy range 40-188 MeV, in order to form a basis whereby proton displacement effects in GaAs structures can be predicted. It is shown that results obtained for 10 MeV protons, for example, can be used to predict results to be expected at much higher energies. >

Multiple-Bit Upset in 130 nm CMOS Technology

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

An investigation of the origins of the variable proton tolerance in multiple SiGe HBT BiCMOS technology generations

This paper presents the first investigation of the physical origins of the observed variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. We use the combination of an extensive set of newly measured proton data on distinct SiGe HBT BiCMOS technology generations, detailed calibrated 2-D MEDICI simulations for both the SiGe HBT and Si CMOS devices, as well as reverse-bias emitter-base and forward-bias electrical stress data to aid the analysis. We find that the scaling-induced increase in the emitter-base electric field under the spacer oxide in the SiGe HBT is primarily responsible for the degraded radiation tolerance with technology scaling, while the decrease in shallow-trench thickness is largely responsible for the improved nFET radiation tolerance with technology scaling.

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Evidence for angular effects in proton-induced single-event upsets

Historically, proton-induced single-event effects (SEES) ground test data are collected independent of the orientation of the microelectronic device to the proton beam direction. In this study, we present experimental and simulation evidence that shows an effect of over an order of magnitude on the proton-induced single-event upset (SEU) cross section when the angle of incidence of the proton beam is varied. The magnitude of this effect is shown to depend on the incidence proton energy and the device critical charge. The angular effect is demonstrated for Silicon-On-Sapphire and Silicon-On-Insulator technologies, but would not necessarily be limited to these technologies.