Gurtej S. Sandhu

Scaling limits of resistive memories.

This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive switching are based on atomic rearrangements in a material. The three model cases are: (1) formation of a continuous conductive path between two electrodes within an insulating matrix, (2) formation of a discontinuous path of conductive atoms between two electrodes within an insulating matrix and (3) rearrangement of charged defects/impurities near the interface between the semiconductor matrix and an electrode, resulting in contact resistance changes. The authors argue that these three model mechanisms or their combinations are representative of the operation of all known resistive memories. The central question addressed in this paper is: what is the smallest volume of matter needed for resistive memory? The two related tasks explored in this paper are: (i) resistance changes due to addition or removal of a few atoms and (ii) stability of a few-atom system.

Metalorganic chemical vapor deposition of TiN films for advanced metallization

Titanium nitride (TiN) films are used extensively in advanced metallization schemes for ultralarge scale integrated applications. In the present experiments, physical properties of thin TiN films deposited using low pressure chemical vapor deposition from tetrakis‐dimethyl‐amino titanium and ammonia have been investigated. Deposited films were characterized by resistivity, stoichiometry and etch rates. It was found that bulk resistivity correlated to wet etch rates with high resistivity films having higher wet etch rates. High bulk resistivity films were unstable in atmosphere and Auger analysis showed higher relative oxygen content. It is concluded that high resistivity films are low density and thereby susceptible to ex situ contamination. Optimized films had bulk resistivity of 250 μΩ cm and wet etch rates comparable to reactively sputtered TiN.

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.

Nucleic acid memory

Nucleic acid memory has a retention time far exceeding electronic memory. As an alternative storage media, DNA surpasses the information density and energy of operation offered by flash memory.

Leakage mechanisms and dielectric properties of Al2O3/TiN-based metal-insulator-metal capacitors

We characterized thin Al2O3 dielectrics with TiN electrodes in a three-dimensional, high-aspect-ratio, metal–insulator–metal capacitor structure. Transmission electron microscopy images did not reveal any interfacial layer(s) or intermixing of the films. This was confirmed by series capacitance analysis. Extensive electrical characterization indicated a well-behaved dielectric response. Time and frequency domain measurements did not show any significant dielectric relaxation. Charge transport was controlled by a direct tunneling mechanism in the field range of 1.5 to 6 MV/cm for a 50 A film. The Fowler–Nordheim tunneling mechanism dominated the high field range (>6 MV/cm for a 50 A film), and the leakage currents became independent of dielectric thickness. The electron tunneling effective mass was found to be 0.2 me.

Process technology and integration challenges for high performance interconnects

Abstract Interconnect metallization for 0.18 μ m technology presents many new challenges for the process technologies. The DRAM device architecture imposes severe requirements of shallow junctions and narrow line widths, which combine to put constraints on the thermal budget while requiring low RC time constant for the interconnects. A number of new materials, such as TiSi x , TiN, W, WN, Pt, and Ru are under consideration for interconnect and capacitor plate metallization. These materials need to provide low resistance lines, be thermally stable, and have no deleterious effects on the gate oxide and capacitor dielectric, and they must be compatible with the overall process flow. Deposition processes for interconnect materials as well as interlevel dielectrics with superior conformality are necessary for a complete fill without voids. A review of the requirements for a manufacturable interconnect scheme and the limitations of the current technology is presented.

Integration of silicon photonics in bulk CMOS

The first monolithic process flow integrating silicon photonics on operational bulk CMOS has been developed. Features include deep-trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables Tx/Rx operation while minimizing interconnect parasitics. With the addition of an external 1280nm source, a fully functional optical link (5Gb/s 2.8pJ/b), capable of wavelength division multiplexing, has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically-integrated Silicon-Germanium selective epitaxial growth based photodetector was developed.

Antireflection coatings for advanced semiconductor device metallization using laser reflow and chemical mechanical planarization

We have investigated titanium tungsten (TiW), titanium nitride (TiN), and chemical vapor deposited (CVD) tungsten (W) films as antireflection coatings (ARC) on aluminum (Al) alloy films to widen the laser planarization process window for contact via filling. ARCs lowered the minimum laser fluence required to accomplish complete contact filling and the maximum laser fluence before the onset of optical ablation, resulting in a significant increase in the process window. This increase closely correlated with the optical and thermal properties of the ARCs. The observed increase in resistivity of laser processed Al films due to intermixing with the ARCs does not preclude its use as via stud metal. A newly developed Al plug technology utilizing chemical mechanical polishing to remove the laser processed film from the surface is presented.

Cu impurity in insulators and in metal-insulator-metal structures: Implications for resistance-switching random access memories

We present numerical results from atomistic simulations of Cu in SiO2 and Al2O3, with an emphasis on the thermodynamic, kinetic, and electronic properties. The calculated properties of Cu impurity at various concentrations (9.91 × 1020 cm−3 and 3.41 × 1022 cm−3) in bulk oxides are presented. The metal-insulator interfaces result in up to a ∼4 eV reduction in the formation energies relative to the crystalline bulk. Additionally, the importance of Cu-Cu interaction in lowering the chemical potential is introduced. These concepts are then discussed in the context of formation and stability of localized conductive paths in resistance-switching Random Access Memories (RRAM-M). The electronic density of states and non-equilibrium transmission through these localized paths are studied, confirming conduction by showing three orders of magnitude increase in the electron transmission. The dynamic behavior of the conductive paths is investigated with atomistic drift-diffusion calculations. Finally, the paper conclud...

Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory

Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.