Roy Meade

Scaling limits of resistive memories.

This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive switching are based on atomic rearrangements in a material. The three model cases are: (1) formation of a continuous conductive path between two electrodes within an insulating matrix, (2) formation of a discontinuous path of conductive atoms between two electrodes within an insulating matrix and (3) rearrangement of charged defects/impurities near the interface between the semiconductor matrix and an electrode, resulting in contact resistance changes. The authors argue that these three model mechanisms or their combinations are representative of the operation of all known resistive memories. The central question addressed in this paper is: what is the smallest volume of matter needed for resistive memory? The two related tasks explored in this paper are: (i) resistance changes due to addition or removal of a few atoms and (ii) stability of a few-atom system.

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.

High- Q CMOS-integrated photonic crystal microcavity devices

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the formers low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process

We present measurements on resonant photodetectors utilizing sub-bandgap absorption in polycrystalline silicon ring resonators, in which light is localized in the intrinsic region of a p+/p/i/n/n+ diode. The devices, operating both at λ=1280 and λ=1550  nm and fabricated in a complementary metal-oxide-semiconductor (CMOS) dynamic random-access memory emulation process, exhibit detection quantum efficiencies around 20% and few-gigahertz response bandwidths. We observe this performance at low reverse biases in the range of a few volts and in devices with dark currents below 50 pA at 10 V. These results demonstrate that such photodetector behavior, previously reported by Preston et al. [Opt. Lett. 36, 52 (2011)], is achievable in bulk CMOS processes, with significant improvements with respect to the previous work in quantum efficiency, dark current, linearity, bandwidth, and operating bias due to additional midlevel doping implants and different material deposition. The present work thus offers a robust realization of a fully CMOS-fabricated all-silicon photodetector functional across a wide wavelength range.

Depletion-mode polysilicon optical modulators in a bulk complementary metal-oxide semiconductor process.

We demonstrate depletion-mode carrier-plasma optical modulators fabricated in a bulk complementary metal-oxide semiconductor (CMOS), DRAM-emulation process. To the best of our knowledge, these are the first depletion-mode modulators demonstrated in polycrystalline silicon and in bulk CMOS. The modulators are based on novel optical microcavities that utilize periodic spatial interference of two guided modes to create field nulls along waveguide sidewalls. At these nulls, electrical contacts can be placed while preserving a high optical Q. These cavities enable active devices in a process with no partial silicon etch and with lateral p-n junctions. We demonstrate two device variants at 5 Gbps data modulation rate near 1610 nm wavelength. One design shows 3.1 dB modulation depth with 1.5 dB insertion loss and an estimated 160 fJ/bit energy consumption, while a more compact device achieves 4.2 dB modulation depth with 4.0 dB insertion loss and 60 fJ/bit energy consumption. These modulators represent a significant breakthrough in enabling active photonics in bulk silicon CMOS--the platform of the majority of microelectronic logic and DRAM processes--and lay the groundwork for monolithically integrated CMOS-to-DRAM photonic links.

Integration of silicon photonics in bulk CMOS

The first monolithic process flow integrating silicon photonics on operational bulk CMOS has been developed. Features include deep-trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables Tx/Rx operation while minimizing interconnect parasitics. With the addition of an external 1280nm source, a fully functional optical link (5Gb/s 2.8pJ/b), capable of wavelength division multiplexing, has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically-integrated Silicon-Germanium selective epitaxial growth based photodetector was developed.

Cu impurity in insulators and in metal-insulator-metal structures: Implications for resistance-switching random access memories

We present numerical results from atomistic simulations of Cu in SiO2 and Al2O3, with an emphasis on the thermodynamic, kinetic, and electronic properties. The calculated properties of Cu impurity at various concentrations (9.91 × 1020 cm−3 and 3.41 × 1022 cm−3) in bulk oxides are presented. The metal-insulator interfaces result in up to a ∼4 eV reduction in the formation energies relative to the crystalline bulk. Additionally, the importance of Cu-Cu interaction in lowering the chemical potential is introduced. These concepts are then discussed in the context of formation and stability of localized conductive paths in resistance-switching Random Access Memories (RRAM-M). The electronic density of states and non-equilibrium transmission through these localized paths are studied, confirming conduction by showing three orders of magnitude increase in the electron transmission. The dynamic behavior of the conductive paths is investigated with atomistic drift-diffusion calculations. Finally, the paper conclud...

Integration of silicon photonics in a bulk CMOS memory flow

Monolithically integrated silicon photonic (SiP) devices have been demonstrated using a modified bulk CMOS flow. Integration was achieved by nominally extending existing process and design collateral without shifting the CMOS parameterization.

Multi-modal optical microcavities for loss avoidance

We demonstrate optical microcavities wherein multiple guided modes interfere to avoid scattering loss at sidewall contacts. Cavities with 62 direct silicon contacts show resonances with intrinsic quality factors near 40,000 across an 80nm spectral range.

Microscopic aspects of the variations in the retention times of dynamic random access memory

The authors have examined the retention time of memory bits. Silicon dangling bond defects are shown to be consistent with retention time observations. Interactions between hydrogen and silicon dangling bond defect complexes are calculated for several model cases using first-principles density functional theory. Variable retention time is explained in terms of hydrogen interacting with a silicon dangling bond defect at the Si–SiO2 interface.