Gustavo Wilke

Clock Distribution Architectures: A Comparative Study

This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty

Non-uniform clock mesh optimization with linear programming buffer insertion

Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.

Analyzing Timing Uncertainty in Mesh-based Clock Architectures

Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one problem with the mesh architectures is the difficulty in accurately analyzing large instances. Furthermore, variations in process and temperature, supply noise and crosstalk noise cause uncertainty in the delay from clock source to flip-flops. In this paper, we study the problem of analyzing timing uncertainty in mesh-based clock architectures. We propose solutions for both pure mesh and (mesh + global-tree) architectures. The solutions can handle large design and mesh instances. The maximum error in uncertainty values reported by our solutions is 1-3ps with respect to the golden Monte Carlo simulations, which is at most 0.5% of the nominal clock latency of about 600ps

Revisiting automated physical synthesis of high-performance clock networks

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

A transistor sizing method applied to an automatic layout generation tool

This paper presents a method of transistor sizing, integrated to a row-based automatic layout generation tool. Automatic layout generation is able to generate a more optimized layout in relation to the standard cell approach because standard cell libraries present a limited number of cells. Most transistor sizing algorithms propose continuous sizing according to the performance constraints and hence cannot be applied in row-based layouts. In this paper, transistors are folded to keep the row height, discretely sizing the transistor. In order to save the final area of the circuit, only transistors in the longest sensitizable paths are sized. The efficiency of the algorithm is measured in relation to area and delay.

High-performance clock mesh optimization

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits

Partitioning algorithms are responsible for the assignment of the random logic blocks and ip blocks into the different tiers of a 3D design. Cells partitioning also helps to reduce the complexity of the next steps of the physical synthesis (placement and routing). In spite of the importance of cells partitioning for the automatic synthesis of 3D designs it has been performed in the same way as in 2D designs. Graph partitioning algorithms are used to divide the cells into the different tiers without accounting for any tier location information. Due to the single dimensional alignment of the tiers connections between the bottom and top tiers have to go through all the tiers in between, e. g., in a design with five tiers a connection between the top and the bottom tiers would require four 3D-vias. 3D vias are costly in terms of routing resources and delay and therefore must be minimized. This paper presents a methodology for reducing the number of 3D-vias during the circuit partitioning step by avoiding connections between non-adjacent tiers. Our algorithm minimizes the total number of 3D-vias while respecting area balance, number of tiers and I/O pins balance. Experimental results show that the number of 3D-vias was reduced by 19%, 17%, 12% and 16% when benchmark circuits were designed using two, three, four and five tires.

A novel scheme to reduce short-circuit power in mesh-based clock architectures

Meshes are widely used for distributing clock in high performance designs. In the past, they were used exclusively for microprocessors, now they are being integrated into the ASIC design flow as well. A mesh has a much smaller skew and jitter, but the high power consumption limits its applicability. In this work, we address the high power consumption of mesh architectures. We propose a novel design for mesh buffers to minimize the short circuit current caused by the different arrival times of the clock signal at mesh buffer inputs. By reducing the short circuit current, we show that the mesh power consumption is reduced by up to 59% and skew by 22%.

A study on layout quality of automatic generated cells

Breaking-through algorithms have been proposed in the latest years enabling the new paradigm of library-free automatic layout synthesis. Library-free synthesis is known to achieve a huge reduction in the number of transistors required to implement a circuit, reducing leakage power consumption. On the other hand, automatic-generated cells are expected to have a larger area than designed-by-hand ones. In this paper we evaluate the layout quality of an automatic generated cell library by ASTRAN, showing that even reducing the set of cells to the ones available in a commercial cell library, the cells generated by our tool gives a better result than the library ones. Our experiments suggests that, although the automatic generated cells layout is less dense, therefore having larger cell areas, timing and power are similar and input capacitances are smaller. Those characteristics result in a design with a speed increased by 12% in average and with a 24% in average smaller power consumption in our test cases.

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction

This paper presents a new buffer sizing methodology for clock meshes. Mesh buffers are usually sized according to the load present in its vicinity. This approach targets at equalizing mesh buffer propagation delays and hence minimizing clock skew. We show that this approach is not well suited when clock signal presents different arrival times at the mesh buffer inputs (i.e. global clock network skew is not zero). Two mesh buffer sizing algorithms are proposed. The first one sizes clock mesh buffers according to the estimated clock arrival time at each mesh buffer input while the second method considers the probability of the clock signal arrival time be within a certain interval. Our experiments show that clock skew can be improved in 8.5% and clock mesh power consumption reduced in 20%.