Hyeong-Sun Hong

Novel 4F 2 DRAM cell with Vertical Pillar Transistor(VPT)

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

The conventional source/drain series resistance (<i>R</i>_sd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in <i>Id</i> and there is insufficient physical modeling. In this letter, we propose a modified <i>R</i>_sd extraction method that uses an optimized <i>Id</i> equation and a threshold voltage (<i>V</i>_th) extraction procedure for NWFETs. The <i>Id</i> equation is modified for the geometry of the NWFET, and <i>V</i>_th is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified <i>Id</i> equations to NWFETs. Therefore, <i>R</i>_sd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (<i>d</i>_NW) when normalized by <i>d</i>_NW, indicating that the extension resistance is the dominant component in the total <i>R</i>_sd.

Effective work function engineering for a TiN/XO(X = La, Zr, Al)/SiO2 stack structures

In this study, we demonstrated that work function engineering is possible over a wide range (+200 mV to −430 mV) in a TiN/XO (X = La, Zr, or Al)/SiO2 stack structures. From ab initio simulations, we selected the optimal material for the work function engineering. The work function engineering mechanism was described by metal diffusion into the TiN film and silicate formation in the TiN/SiO2 interface. The metal doping and the silicate formation were confirmed by transmission electron microscopy and energy dispersive spectroscopy line profiling, respectively. In addition, the amount of doped metal in the TiN film depended on the thickness of the insertion layer XO. From the work function engineering technique, which can control a variety of threshold voltages (Vth), an improvement in transistors with different Vth values in the TiN/XO/SiO2 stack structures is expected.

The cell pattern correction through design-based metrology

Starting with the sub 2Xnm node, the process window becomes smaller and tighter than before. Pattern related error budget is required for accurate critical-dimension control of Cell layers. Therefore, lithography has been faced with its various difficulties, such as weird distribution, overlay error, patterning difficulty etc. The distribution of cell pattern and overlay management are the most important factors in DRAM field. We had been experiencing that the fatal risk is caused by the patterns located in the tail of the distribution. The overlay also induces the various defect sources and misalignment issues. Even though we knew that these elements are important, we could not classify the defect type of Cell patterns. Because there is no way to gather massive small pattern CD samples in cell unit block and to compare layout with cell patterns by the CD-SEM. The CD- SEM is used in order to gather these data through high resolution, but CD-SEM takes long time to inspect and extract data because it measures the small FOV. (Field Of View) However, the NGR(E-beam tool) provides high speed with large FOV and high resolution. Also, it’s possible to measure an accurate overlay between the target layout and cell patterns because they provide DBM. (Design Based Metrology) By using massive measured data, we extract the result that it is persuasive by applying the various analysis techniques, as cell distribution and defects, the pattern overlay error correction etc. We introduce how to correct cell pattern, by using the DBM measurement, and new analysis methods.

Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide

In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 µm in 0.11 µm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.

Crystallization Time and High Resolution Electron Microscope Lattice Images of Phase Change Optical Discs Dynamically Laser-Annealed

It was demonstrated that a dynamic laser-annealing system (DLAS) could be used for obtaining the crystallization time (tx) for the phase change optical discs. In the DLAS, the laser beams are irradiated onto the discs which are rotating at variable linear velocity (V) with variable power. The measured crystallization time (tx) for the disc ZnS–SiO2/Ge2Sb2.5Te5/ZnS–SiO2/Al–Ti (disc A) monotonously decreased from 480 ns to 206 ns as the laser power increased from 300 mW to 900 mW. tx for Ge2Sb2Te5/ZnS–SiO2 (disc B) more sharply reduced from 400 ns to 200 ns than that for the disc A as the power increased from 200 mW to 400 mW. In the case of the disc B, tx was determined to be 50 ns at an extrapolated 570 mW. The high resolution electron microscope (HREM) of the cross sectional lattice image revealed that the dominant crystallized phase in the active Ge2Sb2Te5 layer was the stoichiometric GeTe. The measured inter-planar spacing of 0.298 nm corresponded to the (202) plane. The Kink bands and edge dislocations were also observed in the crystallized active layer. This was attributed to the thermal stress due to the thermal expansion difference between the active layer and the dielectric layer.

A novel method to characterize DRAM process variation by the analyzing stochastic properties of retention time distribution

This study proposes an innovative method to measure the variation of cell leakage current. Extreme cell leakage determines DRAM refresh time (tREF). Although the average leakage current from the test element group (TEG) has been the only index for determining cell leakage, it does not provide the distribution of unit cell leakage. We find that cell leakage distribution can be calculated from the slope at the retention time-fail bit plot. A steep slope indicates a small cell leakage distribution that corresponds to a long tREF. It is proved with statistical models and experimental results with mass data.

In-Depth Analysis of NBTI at 2X nm Node DRAM

An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling the heat-budget at BEOL shows a promising result in NBTI lifetime, but it is not appropriate for DRAM process since it decreases the refresh time. Next, the buried SiGe channel p-MOSFET, which has 1.2 times higher NBTI immunity, is considered but difficult to adopt in DRAM peripheral circuit due to extra manufacturing cost. Finally, a deuterium annealing seems to be the right candidate for DRAM process since it improves the NBTI immunity without the refresh time penalty. This NBTI gain, however, varies depending on the amount of deuterium atom at Si/SiON interface and the probability of Si-D bond replacement with Si-H bond. Thus, selecting a right process sequence and an annealing condition is crucial.

Free energy modeling of block-copolymer within pillar confinements on DSA lithography

To a major candidate and beyond, directed self-assembly (DSA) lithography is investigated on DRAM contact-hole fabrication. We perform a systematic study about behavior of asymmetric PS-b-PMMA block copolymers (BCP) within pillar confinement for DSA and find that selectively removed PMMA contact domain has a different morphology according to chemically modified pillar surfaces. We calculate the perturbation of PMMA contacts by pillar diameter using free energy magnitude model. This established model provides practical engineering insight for present pillar scheme and future graphoepitaxial self-assembly techniques for semiconductor DSA procedure.

The improvement of HEIP immunity using STI engineering at DRAM

Abstract The increase of standby current of DRAM caused by the HEIP degradation of p-MOSFET and the way to improve the HEIP immunity without the deterioration of performance are reported. The electron trapping at the top region of STI SiN liner is the main cause of the HEIP degradation. To improve the HEIP immunity, several candidates are examined. The large tabbed-gate device and the thicker STI sidewall oxide are not proper for DRAM due to the decreases of Ion and the refresh time, respectively. The thin poly Si liner, which is inserted between the STI sidewall oxide and the SiN liner, acts as an immune layer against the HEIP degradation. So, the poly Si liner scheme can be a good solution to improve the HEIP immunity without the deterioration of DRAM performance.