Yoo-Sang Hwang

Novel 4F 2 DRAM cell with Vertical Pillar Transistor(VPT)

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.

A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyond

A new DRAM cell scheme using merged process with storage node and memory cell contact called BC is introduced for free alignment tolerance between memory cell contact and storage node. The new cell scheme and conventional COB stacked cell scheme are compared for the misalignment tolerance and photo and etch process issues. The new cell scheme is processed in 0.15 /spl mu/m minimum feature size and its results are described including vertical SEM pictures, capacitance-voltage data, and leakage current. This new cell scheme achieved the requirement of memory cell capacitance of 25 fF/cell in 0.30 /spl mu/m pitched 4 Gb DRAMs.

Novel Deep Trench Buried-Body-Contact (DBBC) of 4F 2 cell for sub 30nm DRAM technology

Novel Deep Trench Buried-Body-Contact (DBBC) has been successfully developed for 4F2 DRAM cells on sub-30nm technology node. The critical requirements of thermal stability, shallow junction depth, and conformal source-drain doping profile for the contact are achieved by using an ultra thin Ti silicide ohmic layer and PLAD technique, which also show excellent electrical performance and process feasibility for the development of 4F2 DRAM cell on the 30nm node and beyond.