Gyoocheol Hwang

A capacitive touch controller robust to display noise for ultrathin touch screen displays

Capacitive touch screens have become widely adopted in mobile applications. Capacitive touch-screen display modules have conventionally been assembled by bonding two separate modules: 1) a touch-screen module with touch panel glass or film attached to the cover window, and 2) a display module, with a small air gap between them. An important role of the air gap is to decrease capacitive coupling of display noise to the sensors, and it is very effective since permittivity of air is more than 4χ lower than that of glass.

A 1 GHz Alpha microprocessor

A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is highly leveraged from an existing 0.35 /spl mu/m, 6-way issue, 6 metal layer implementation with wire-bond packaging technology. The chip contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 kB 2-way set associative dual-ported data cache.

A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface

A fast locking 3.0 Gb/s clock data recovery circuit (CDR) based on the digital DLL is proposed for intra-panel clock-embedded display interface. The CDR uses 3-level sub-ranging delay control in digital DLL. Overlapping range selection, successive approximation, and highly-linear timing amplifier are used for most, intermediate, and least significant bits of control, respectively to improve both jitter immunity and dynamic range of digital DLL. The designed chip occupies 0.076 mm2 active area in 0.13μm CMOS technology and consumes 6.72 mW at 3.0 Gb/s from a 1.2 V supply. The rms and pk-to-pk jitters of the recovered clock are as small as 4.8 ps and 30.8 ps, respectively.

eDRAM-based tiered-reliability memory with applications to low-power frame buffers

Embedded DRAM (eDRAM) is becoming more and more popular as a low-cost alternative to on-chip SRAM. eDRAM is particularly attractive for frame buffers in video applications with ever increasing screen resolutions. However, eDRAM suffers short retention time and high refresh power, which prevents its widespread adoption. To save the refresh power of eDRAM-based frame buffers, we propose Tiered-Reliability Memory (TRM), where the frame buffer is divided into multiple segments with different refresh periods and hence different error rates. By allocating most-significant bits to the most reliable segment, our four-tier TRM reduces refresh power by 48% without degrading user experience.

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

Emerging applications like cloud computing require high-speed low-latency access to high-volume data. In these applications, use of memory modules having multi-drop channels may be needed for time-efficient access to high-density memory data. A key design issue here is how to let interface transceivers not be affected by ISI and reflection noise generated by multi-drop channels having imperfect termination. The current-integrating decision-feedback equalizer (DFE) [1], which can cancel both high-frequency noise and post-cursor ISI simultaneously, has a limitation due to high gain-boosting and/or tap weight over-emphasis in equalizers to avoid eye closure caused by ISI-referred input pattern dependency. Duobinary signaling [2], which requires less boosting for equalizers by taking advantage of channel roll-off characteristic, is not effective in a multi-drop channel application because even a small timing or waveform variation due to high-frequency noise may cause degradation of the quality of duobinary signals. This work presents an integrating duobinary-based DFE receiver to avoid drawbacks described above and to increase the effective-data rate of multi-drop channels. A synergistic combination between the integrating equalizer and the duobinary signaling can provide advantages such as 1) lower gain-boosting for equalizers, 2) no need for precursor equalization, 3) ideally no input-pattern dependency during integration, 4) being more robust to high-frequency noise, 5) alleviated DFE critical timing, and 6) embedding DFE taps into duobinary circuits.

Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction

Line inversion-based mobile TFT-LCD driver IC with novel quadruple-gamma-curve correction is presented. The driver IC allows for a cost-effective accurate curve correction for multiple gamma values of γ^1.0, γ^1.8, γ^2.2, and γ^2.5 by adopting novel voltage-symmetric gray curve synthesis and variable reference resistor-tap biasing schemes. A test chip in a 6 V/0.7-μm triple-well CMOS process indicated a gray voltage error of ±8 mV with gray-to-gray error difference under ±3 mV.

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

This paper describes a 5.8 Gb/s adaptive integrating duobinary decision-feedback equalizer (DFE) for use in next-generation multi-drop memory interface. The proposed receiver combines traditional interface techniques like the integrated signaling and the duobinary signaling, in which the duobinary signal is generated by current integration in the receiver. It can address issues such as input data dependence during integration, need for precursor equalization, high equalizer gain boosting, and sensitivity to high-frequency noise. The proposed receiver also alleviates DFE critical timing to provide gain in speed, and embed DFE taps in duobinary decoding to provide gain in power and area. The adaptation for adjusting the equalizer common-mode level, duobinary zero level, tap coefficient values, and timing recovery is incorporated. The proposed DFE receiver was fabricated in a 45 nm CMOS process, whose measurement results indicated that it worked at 5.8 Gb/s speed in a four-drop channel configuration with seven slave ICs, and the bathtub curve shows 36% open for

Analysis on panel power consumption of mobile TFT-LCDs based on line inversion driving

10^{-10}

A characterization method for projected capacitive touch screen panel using 3-port impedance measurement technique

bit error rate.

Memory System and Memory Management Method Including the Same

This paper analyzes and compares the penal power consumption for mobile TFT-LCDs. Three representative penal driving schemes (the basic data driving, the charge-recycling data driving, and the stepwise data driving) based on the line inversion driving method are considered in this analysis, and equations for representing the penal power consumption of respective driving schemes are derived. This is the first to analyze the panel power consumption of line inversion-based mobile TFT-LCDs including parasitic capacitance effect. The analysis procedure presented here is helpful for power study, and gives benefits of providing accurate estimation of the total power consumption of mobile TFT-LCDs driven a line inversion driving.