Kyung-Suc Nah

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

A GSM/EGSM/DCS/PCS direct conversion receiver with integrated synthesizer

A global system for mobile communications direct conversion receiver with an integrated synthesizer is implemented with a 0.35-mum BiCMOS technology. Proposed second-order intercept point calibration method is analyzed and verified by measurements. The maximum IIP2=66 dBm is achieved by an 8-b resistive calibration code. The receiver draws 57/63 mA from a 2.7-V supply

A 2-GHz wide band low phase noise voltage-controlled oscillator with on-chip LC tank

A 2 GHz wide band low phase noise voltage-controlled oscillator (VCO) is presented. To achieve excellent phase noise performance while maintaining wide band frequency tuning characteristic, a 6-bit digitally controlled switched-capacitor bank and tail current control scheme are used. The effect of the gate length of the MOS switches on the Q-factor of the LC tank is also analysed qualitatively. The measured phase noise is -115 dBc/Hz at an offset frequency of 100 kHz from a 2 GHz operating frequency. The total tuning range is as wide as 550 MHz (30%) and the measured RF output power is about -10 dBm at the single ended output buffer. The VCO gain varies from 21 MHz/V to 45 MHz/V for the entire operating frequency. The VCO is implemented using a 0.5 /spl mu/m SiGe BiCMOS process.

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate wideband frequency range, a switched capacitor bank LC tank VCO and an adaptive frequency calibration (AFC) technique are used. A 3-bit 4th order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3Hz as well as agile switching time. The experimental results show -80dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129dBc/Hz out-of-band phase noise at 400kHz-offset frequency. The fractional spurious is less than -70dBc/Hz at 300kHz offset frequency and the reference spur is -75dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.

A 2.6 V GSM/PCN dual band variable gain low noise RF down conversion mixer

As a building block for a GSM/PCN dual band RF transceiver IC, a low noise variable gain RF down conversion mixer is designed and fabricated using a 15 GHz-f/sub T/, 0.5 /spl mu/m 3-metal 2-poly BiCMOS process. Careful consideration is paid to the low noise performance of the mixer. Moreover, using constant-impedance input/output stages, RF input and IF output return losses are maintained under -16 dB for both high and low gain modes. Measured gain and DSB noise figure of the mixer are 10.9 dB and 9.1 dB, respectively, for GSM band, and 9.6 dB and 8.1 dB, respectively, for PCN band. Gain difference between high and low gain modes is 11 dB and 11.8 dB for GSM and PCN, respectively. Total DC currents are 13 mA for GSM and 11.5 mA for PCN from a 3 V supply voltage. Mixer performance is maintained with supply voltage down to 2.6 V.

43.2: A 400Mbps/ch SiDP Receiver for Mobile TFT-LCD Driver IC

A high speed serial interface receiver is realized in a 0.18um high voltage CMOS technology for a mobile 24-bit hVGA TFT-LCD driver (LDI) IC. The type of serial interface implemented is called Simple Display Port (SiDP) and is intended to replace the legacy RGB interface in the LDI ICs. The receiver consists of one clock and two data channels, and thereby reduces the number of signal lines going through the hinge of a mobile phone from 28 down to 6. All channels conform to Sub Low-Voltage Differential Signaling (SubLVDS) convention. The total transfer rate can be up to 800Mbps for two data channel. The current consumption was 5.4mA at the data rate of 600Mbps.

A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDs

A single-chip 16.7M color VGA display driver IC featuring partial graphic RAM and 500Mb/s/ch high-speed serial interface has been developed. It pairs with a 1.98-inch mobile VGA amorphous-silicon TFT-LCD panel with 400 pixels/in. The IC has been fabricated in a 0.18 mum triple-well CMOS process with high-voltage transistors and occupies 23.0 times 2.5 mm2. The chip has two supplies, 1.8 and 2.75V, and uses a total of 45mW.

A 50-MHz 98-dB dynamic-range dB-linear programmable-gain amplifier with 2-dB gain steps for 3-V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98-dB with 2-dB gain steps and is controlled by 6-bit gain control bits for a 3-V power supply. It has been fabricated in a 0.5-/spl mu/m 15-GHz f/sub T/ Si BiCMOS process and draws a constant current of 13-mA, independent of the gain settings. The active die area taken up by the circuit is 400-/spl mu/m /spl times/1170-/spl mu/m. A noise figure (NF) of 5-dB was measured at the maximum gain setting.

A /spl Sigma/-/spl Delta/ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

This paper presents a fractional-N synthesizer with a 3-bit 4th-order interpolative /spl Sigma/-/spl Delta/ modulator for a GSM/GPRS direct conversion transceiver. With an integrated VCO and an integrated loop filter, the synthesizer achieves the phase noise performances less than -78dBc/Hz at close-in offset and less than -116dBc/Hz at 400kHz offset. The chip was fabricated and evaluated in a 0.35 /spl mu/m SiGe BiCMOS process.