Gyu-Seog Cho

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

Advanced DC-SF Cell Technology for 3-D NAND Flash

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.

Characterization of Polymetal Gate Transistors With Low-Temperature Atomic-Layer-Deposition-Grown Oxide Spacer

In this letter, W/WNx/poly-Si gate DRAM transistors with oxide spacers grown by low-temperature atomic layer deposition (ALD) have been fabricated, and the electrical characteristics are analyzed. The low-temperature ALD oxide effectively prevents the oxidation of exposed tungsten, and the fabricated devices show superior electrical properties to those with nitride/oxide spacer. The data retention time is improved by 30%, and the hot-carrier degradation characteristics are also enhanced. The threshold voltage of the fabricated W/WNx/poly-Si gate n-channel transistors with ALD oxide spacer is increased due to the suppression of boron deactivation by hydrogen. In particular, the transconductance of n-channel transistors in core/peripheral circuits was found to be enhanced by less-compressive stress in ALD oxide spacers.

Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

The effects of three types of program (PGM) disturbance, which are X, XY, and Y mode, on the chip level erase (ERS) threshold voltage (VT) distribution in three-dimensional (3D) NAND Flash memory were studied. A simple model was constructed to emulate both the chip operation and PGM characteristics. It was found that the right tail and peak of ERS VT distribution after PGM operation of a physical block are determined by Y mode and other two modes respectively. We concluded that the difference in channel (CH) boosting level between Y mode and other two modes should be achieved less than a width of initial ERS VT distribution in order not to degrade its right tail. The optimal PGM operation conditions for high CH boosting level were proposed to minimize the band-to-band tunneling (BTBT) current in the dummy WL region.

Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory

Abnormal cell-to-cell interference occurring in NAND flash memory has been investigated. In the case of extremely downscaled NAND flash memory, cell-to-cell interference increases abnormally. The abnormal cell-to-cell interference has been observed in a p-type floating gate (FG)/control gate (CG) cells for the first time. It has been found that the depletion region variation leads to the abnormal cell-to-cell interference. The depletion region variation of FG and CG is determined by state of neighbor cells. The depletion region variation affects CG-to-FG coupling capacitance and threshold voltage variation (ΔVT). Finally, it is observed that there is a symmetrical relationship between n- and p-type FG/CG NAND flash memory in terms of cell-to-cell interference.

GaAs/AlGaAs Lensed Light Emitting Diode by the Meltback and Regrowth in Liquid Phase Epitaxy

AlGaAs micro-lens was fabricated for light emitting diode (LED) applications using the liquid phase epitaxy (LPE) meltback technique. The lenses can be used to enhance the optical power of AlGaAs/GaAs LEDs. The meltback technique using the LPE provides simple fabrication procedures which is not easily achieved in the conventional lensed structure.

Influence of Intercell Trapped Charge on Vertical NAND Flash Memory

The influence of intercell trapped charge (ITC)—the charge trapped at the inter-cell nitride regions by fringe electric fields during program and erase operations—on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradation on VNAND flash memory is discussed, using both simulation and experimental results. A solution for ITC suppression is also proposed: the use of low-k intercell regions.

Investigation of Vertical Channel Architecture for Bulk Erase Operation in Three-Dimensional NAND Flash Memory

A bit-cost scalable (BiCS) technology using a bulk erasing method instead of the conventional erase operation using gate-induced drain leakage (GIDL) is proposed to realize better cell characteristics and process feasibility for three-dimensional (3D) NAND flash memory. This has an additional electrode layer for a bulk erase operation in the middle of a vertical string cell. Here, we confirmed that this structure using an additional electrode provides good program and erasing speed by simulation. Furthermore, junction engineering is performed to realize a polysilicon layer of the flat plate type as a bulk electrode for better design feasibility. From this result, we expect that a bulk erasable BiCS technology using a flat plate erase electrode can be a candidate 3D NAND flash memory technology.

An abnormal floating gate interference and a low program performance in 2y nm NAND flash devices

We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work suggests that the poly-Si depletion of the CG should be controlled and considered utilizing a full 3-dimensional (3D) TCAD process and device simulations to improve the FG interference and the performance of NAND flash device beyond 2y nm technology.