Seokkiu Lee

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

Complementary metal-oxide-semiconductor compatible Al-catalyzed silicon nanowires - Growth and the effects of surface oxidation of Al seeding layer

High-quality single-crystal Si nanowires with diameters ranging from 10 to 200 nm have been successfully grown using Al catalyst via a vapor-liquid-solid mechanism. Critical issues such as the effects of surface oxidation of the Al seeding layer on the growth of Si nanowires and selective removal of metal catalyst after nanowire growth have been systematically studied. Results show that the growth of Si nanowire is strongly dependent on the surface oxidation of Al seeding layers. It is also found that metal-contamination-free Si nanowires can be achieved by selective etching of the remaining Al particles from nanowires, providing a Si nanowire as a complementary metal-oxide-semiconductor compatible building block for future nanoelectronics applications.

Advanced DC-SF Cell Technology for 3-D NAND Flash

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.

Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies

Our Middle-1X nm MLC NAND (M1X) flash cell is intensively characterized with respect to reliability and manufacturability. For the first time, the novel active air-gap technology is applied to alleviate the drop of channel boosting potential of program inhibition mode, BL-BL interference is reduced to our 2y nm node level by this novel integration technology. Furthermore, it also relaxes the effect of process variation like EFH (Effective Field oxide Height) on cell Vt distribution. Better endurance and retention characteristics can be obtained by p+ doped poly gate. By optimization of active air-gap profile and poly doping level, M1X nm MLC NAND flash memory has been successfully implemented with superior manufacturability and acceptable reliability.

Scaling Challenges in NAND Flash Device toward 10nm Technology

The scaling of floating gate cell has been the key driving force in NAND flash market growth over the past two decades. However, the scaling of conventional floating gate technology below 20nm is looking to be very difficult due to some physical and electrical issues. Critical issues of scaling in NAND flash memory technology below 20nm are reviewed. The possible solutions for overcoming scaling challenges are introduced. With these solutions, floating gate NAND flash cell could be shrunk down close to 10nm dimension.

Novel Negative

A novel program-inhibit phenomenon of “negative” cell Vt shift has been investigated for the first time in 2X- 3X-nm self-aligned shallow trench isolation nand Flash memory cells. The negative Vt shift is caused in an inhibit cell when along-word-line adjacent cell is programming. The magnitude of the negative shift becomes larger in the case of higher program voltage (VPGM), lower field oxide height, slower program speed of the adjacent cell, and high Vt of victim cell. The experimental results suggest that the mechanism of negative Vt shift is attributed to hot holes that are generated by FN electron injection from channel/junction to the control gate. This phenomenon will become worse with cell size scaling since hot hole generation is increased by increasing the electron injection due to narrower floating gate space. Therefore, this negative Vt shift phenomenon is one of the new scaling limiters of nand Flash memory cell, which needs to be managed for 2 and 3 b/cell in 2X nm and beyond nand Flash memories.

Vt

The effects of three types of program (PGM) disturbance, which are X, XY, and Y mode, on the chip level erase (ERS) threshold voltage (VT) distribution in three-dimensional (3D) NAND Flash memory were studied. A simple model was constructed to emulate both the chip operation and PGM characteristics. It was found that the right tail and peak of ERS VT distribution after PGM operation of a physical block are determined by Y mode and other two modes respectively. We concluded that the difference in channel (CH) boosting level between Y mode and other two modes should be achieved less than a width of initial ERS VT distribution in order not to degrade its right tail. The optimal PGM operation conditions for high CH boosting level were proposed to minimize the band-to-band tunneling (BTBT) current in the dummy WL region.

Shift Phenomenon of Program–Inhibit Cell in

A novel program disturb phenomena of “negative” cell-Vt shift has been investigated for the first time in 2X∼3X nm Self-Aligned STI cell[1,2] of NAND flash memory. The negative Vt shift occurs on an inhibited cell adjacent to a cell being programmed in the WL direction. The magnitude of the shift becomes larger when the programming voltage (VPgm) is higher, thinner field oxide and slower program speed of the adjacent cell. The mechanism of negative Vt shift is attributed to hot holes that are generated by FN electrons, injected from channel / junction to the control gate (CG) along the isolation. This phenomenon will become worse with scaling since hot hole generation is increased by increasing electron injection due to narrower FG space. Therefore, this negative Vt shift phenomenon is one of the new NAND flash memory cell scaling limiter, that needs to be managed for 2bits and 3bits/cell in 2X nm and beyond.

\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}

As the high performance very-large-scale integration (VLSI) systems operate with high speed and low voltage, the system-level electrostatic discharge (ESD) event is becoming one of the important noise sources causing logic errors and system malfunctions such as system reboot or fault. To understand the ESD noise phenomena and improve the system-level ESD noise immunity for devices, the accurate ESD noise measurement is necessary. In this paper, the measurement and modeling method for system-level ESD analysis is introduced and validated.