Sung-Kye Park

Device considerations for high density and highly reliable 3D NAND flash cell in near future

Recently, we have suggested highly manufacturable and reliable 3D NAND flash cell called “SMArT”[1], which is intended to minimize both stack height and word line resistance. Because the storage node of this cell is charge trap nitride, its device characteristics were far different from conventional floating gate. In this paper, the key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

Highly productive PCRAM technology platform and full chip operation: Based on 4F 2 (84nm pitch) cell scheme for 1 Gb and beyond

We successfully developed highly scalable and cost-effective PCRAM technology based on 0.007um2 (4F2, 84nm pitch) sized novel cell scheme. The chip size and density are 33.207mm2 and 1Gb. The device functionality and reliability were clearly demonstrated through fully integrated chip, which showed a promising feasibility for productive NVM applications.

Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

Read current fluctuation (ΔI_read) due to random telegraph noise was measured from a cell in a NAND flash memory cell string, and its effect on threshold voltage fluctuation (ΔV_th) was analyzed. Sixteen-level fluctuation (four traps) was observed in a 60-nm cell of a cell string (ΔI_read/I_read of ~0.4). ΔI_read increased with decreasing L_g, and ΔI_read/I_read up to 0.75 was observed at 48 nm. ΔI_read, ΔV_th, and their relation were clearly analyzed with program/erase mode of a cell and pass cells in a string. Although ΔI_read is largest when a read cell and pass cells are erased, ΔV_th is largest when a read cell is erased and pass cells are programmed in a cell string. We also observed the specific noise amplitude under various conditions, such as the bit-line bias, the pass bias of unselected cells in the NAND strings, and the temperature.

Advanced DC-SF Cell Technology for 3-D NAND Flash

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

Position-Dependent Threshold-Voltage Variation by Random Telegraph Noise in nand Flash Memory Strings

The position dependence of threshold-voltage change (ΔV_th) in floating-gate NAND Flash cell strings due to random telegraph noise was characterized. It was found that the cumulative distribution of ΔV_ths measured from 100 cell devices at word line 31 (WL31) is broader than that at WL0 due to smaller transconductance (G_m). As the position of a read cell in the string is changed from WL0 to WL31, maximum G_m decreases by ~50% since the equivalent source resistance (R_s) of the read cell increases. Decreasing G_m makes the slope of the I_read - V_read curve low, which increases ΔV_th at the same noise current fluctuation. It was also shown that the G_m (finally, ΔV_th) of a read cell can be changed by controlling the pass bias since the pass bias changes the channel resistance (≈ R_s) of the pass cells.

The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG)

We propose the novel 3-dimensional (3-D) vertical floating gate (FG) NAND flash memory cell arrays with novel electrical source/drain (S/D) technique using Extended Sidewall Control Gate (ESCG). Cylindrical FG structure cell is implemented to overcome the reliability issues of the charge trap cell such as SONOS and TANOS cell. We also propose the novel electrical S/D layer using the ESCG structure to realize the enhancement mode operation. Using this novel structure, we successfully demonstrate the normal flash cell operation with high-speed programming and superior read current due to both the increasing of coupling ratio and low resistive electrical S/D technique. Moreover, we found that the 3-D vertical flash memory cell array with novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with planar FG NAND cell. From above all, the proposed cell array is one of the candidates of Terabit 3-D vertical NAND flash cell array with high-speed read/program operation and high reliability.

Analysis of Random Telegraph Noise and low frequency noise properties in 3-d stacked NAND flash memory with tube-type poly-Si channel structure

Random Telegraph Noise (RTN) and low frequency noise (LFN) properties were investigated for the first time in sub-100 nm 3-D stacked NAND flash memory with tube-type poly-Si channel structure. The 3-D stacked NAND flash memory showed higher noise power density of bit-line (BL) current (IBL) by ~10 times than 32 nm planar NAND flash memory. The behavior of ΔIBL was investigated with control-gate bias (VCG), BL bias (VBL) and pass bias (Vpass). As temperature (T) increases, capture and emission times becomes short. To understand poly-Si channel, planar poly-Si thin film transistors (TFT) with different grain size were prepared and analyzed in terms of noise, subthreshold swing (SS), and T.

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.