H. Ghoneim

Si–InAs heterojunction Esaki tunnel diodes with high current densities

Si–InAs heterojunction p-n diodes were fabricated by growing InAs nanowires in oxide mask openings on silicon substrates. At substrate doping concentrations of 1×1016 and 1×1019 cm−3, conventional diode characteristics were obtained, from which a valence band offset between Si and InAs of 130 meV was extracted. For a substrate doping of 4×1019 cm−3, heterojunction tunnel diode characteristics were obtained showing current densities in the range of 50 kA/cm2 at 0.5 V reverse bias. In addition, in situ doping of the InAs wires was performed using disilane to further boost the tunnel currents up to 100 kA/cm2 at 0.5 V reverse bias for the highest doping ratios.

InAs–Si Nanowire Heterojunction Tunnel FETs

In this letter, we present vertical InAs-Si nanowire heterojunction tunnel FETs (TFETs). The devices consist of an InAs source on a Si channel and drain, with a wraparound gate stack. The Si-InAs combination allows achieving high <i>I</i>_on/<i>I</i>_off ratios above 10⁶, with an <i>I</i>_on of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec measured over three decades of current. Ni alloying of the InAs top contact is shown to improve performance of both diodes and TFETs significantly. The combination of higher doping at the contact and the alloying also leads to an enhanced performance compared with previously published devices.

Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High-

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO₂, Al₂O₃, and HfO₂, and show a performance enhancement when using high-<i>k</i> dielectric materials. The best performance is achieved for the devices using HfO₂ as the gate dielectric, which reach an <i>I</i>_on of 0.1 μA/μm (<i>V</i>_DS = -0.5 V, <i>V</i>_GS = -2 V), combined with an average inverse subthreshold slope (SS) of ~ 120 mV/dec and an <i>I</i>_on/<i>I</i>_off ratio of around 10⁶. For the tunnel FETs with Al₂O₃ as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700°C was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs.

k

In this paper we present vertical tunnel diodes and tunnel FETs (TFETs) based on III-V-Si nanowire heterojunctions. We experimentally demonstrate InAs-Si Esaki tunnel diodes with record high currents of 6 MA/cm² at 0.5 V in reverse bias. Furthermore, we have fabricated vertical InAs-Si nanowire TFETs with gate-all-around architecture and high-k dielectrics. The InAs-Si combination allows achieving high I_on/I_off ratios above 10⁶, with I_on of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec over three decades. The achieved improvements can be attributed to increased nanowire doping and Ni alloying of the top contact. The results indicate the benefits of the InAs-Si material system combining the possibility of achieving high I_on with high I_on/I_off ratio.

Gate Dielectric

In the present work we demonstrate the fabrication of tunneling field-effect transistors (TFETs) based on VLS grown silicon nanowires (Si NWs). We have integrated two different gate stacks, a conventional one using SiO2 and a HfO2 high-k gate stack. The use of a high-k gate dielectric markedly improves the TFET performance in terms of average slope and on-current, Ion. Furthermore, we investigate the low-temperature behaviour of the TFETs.

InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs

In this work we investigate doping by solid-state diffusion from a doped oxide layer, obtained by plasma-enhanced chemical vapor deposition (PECVD), as a means for selectively doping silicon nanowires (NWs). We demonstrate both n-type (phosphorous) and p-type (boron) doping up to concentrations of 10(20) cm(-3), and find that this doping mechanism is more efficient for NWs as opposed to planar substrates. We observe no diameter dependence in the range of 25 to 80 nm, which signifies that the NWs are uniformly doped. The drive-in temperature (800-950 °C) can be used to adjust the actual doping concentration in the range 2 × 10(18) to 10(20) cm(-3). Furthermore, we have fabricated NMOS and PMOS devices to show the versatility of this approach and the possibility of achieving segmented doping of NWs. The devices show high I(on)/I(off) ratios of around 10(7) and, especially for the PMOS, good saturation behavior and low hysteresis.

Comparison of VLS grown Si NW tunnel FETs with different gate stacks

Gated p-i-n diodes operating as tunnel field effect transistors (TFETs) [1] are recently attracting much attention because of potential benefits over conventional MOSFETs. They are expected to have lower off-current, and operate at lower supply voltage compared to MOSFETs. Unfortunately, these promises are very difficult to realize using materials like Si, Ge and its alloys. However, encouraging experimental results were recently obtained using lower bandgap III–V (InGaAs) material systems [2, 3] offering higher tunneling probabilities. Here we report first results on the fabrication and electrical characterization of III–V / Si heterojunction TFETs with InAs as low bandgap source. This material combination maintains the advantages of Si as channel, drain and substrate material as proposed in [4].

Solid-state diffusion as an efficient doping method for silicon nanowires and nanowire field effect transistors

We present a study on suppressing the ambipolar behavior of Schottky barrier metal-oxide-semiconductor field-effect transistors (MOSFET). Inserting a silicon nitride layer of appropriate thickness between the metallic source/drain electrodes and the silicon yields a low Schottky-barrier and simultaneously tunes the properties of the contact from metal-semiconductor-like to the behavior of a doped contact. Moreover, device characteristics of pseudo-MOSFETs reveal an efficient suppression of ambipolar behavior. Comparison with an alternative way of achieving low Schottky-barrier contacts, i.e., by inserting a strong dipole layer such as LiF between the metal and the silicon, reveals that the suppression is not a result of shifting the Fermi level closer to the conduction band but is caused by a reduction of metal-induced gap states. The trade-off between suppression of the ambipolar behavior, contact length and on-state current is investigated with simulations.

Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors

In the present work we demonstrate the successful implementation of tunneling field-effect transistors (TFETs) based on silicon nanowires (Si NWs) that were grown using the vapor-liquid-solid (VLS) growth method. Device optimization resulted in increased band-to-band tunneling with an on-current of 0.5 ¿A/¿m, and Ion/Ioff ratio of about 6 decades combined with an inverse subthreshold slope (SS) of around 100 mV/dec over several decades of current and even sub-60 mV/dec for the lowest currents.

Suppression of ambipolar behavior in metallic source/drain metal-oxide-semiconductor field-effect transistors

We study the suppression of ambipolar behavior of Schottky-barrier MOSFETs using an interface engineering approach. Inserting a thin silicon nitride layer between the metallic source/drain electrodes and the silicon yields low Schottky barriers and results in unipolar device characteristics demonstrated with pseudo-MOSFETs. Simulations support the observed suppression and show that with appropriate silicon nitride thickness the metal-induced-gap states can be suppressed and hence the properties of the contact can be tuned from metal-semiconductor-like to the behavior of a doped-contact. Furthermore, there is a trade-off between suppression of the ambipolar behavior, contact length and on-state current.