H. Haddara

Reconfigurable dual-band dipole antenna on silicon using series MEMS switches

The paper presents a reconfigurable dual-band 4.86 and 8.98 GHz dipole antenna on silicon using series MEMS switches. The effects of series MEMS switches on the antenna performance are studied. The design is performed using the 3D electromagnetic simulator HFSS/sup /spl reg//. Using the designed series MEMS switches, the obtained antenna return loss is -10.2 dB and -21.6 dB, at the lower and upper frequencies, respectively. However, comparable to the case of ideal switches, a frequency shift of 0.4% and of 2.8% at the lower and upper frequencies, respectively, is observed. The antenna, including the MEMS switches, has bandwidth of 1.9% and 13.6% at the lower and upper frequencies, respectively. The antenna directivity is 2 dB at the lower frequency, and is 3 dB at the upper frequency.

Characterization methods for submicron MOSFETs

Preface. 1. Static Measurements and Parameter Extraction. 2. Small Signal Characterization of VLSI MOSFETs. 3. Charge Pumping. 4. Deep Level Transient Spectroscopy. 5. Individual Interface Traps and Telegraph Noise. 6. Characterization of SOI MOSFETs. 7. Modern Analog IC Characterization Techniques. Index.

Implementation of hot-carrier reliability simulation in Eldo

The implementation of all components of hot-carrier reliability simulation in Eldo is described in this paper. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. Two approaches for modeling the degraded MOS transistor have been implemented, namely, the parameter fitting method and a newly proposed /spl Delta/I/sub d/ model. The new model overcomes the discontinuity and subthreshold invalidity of the existing models. The model has proven high accuracy for two well known foundries on their 0.25 /spl mu/m technologies. Simulation is results on some direct applications like inverters and ring oscillator circuits are also presented in this paper.

CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers

Cell-based design using a new D-latch is employed to design a VCO and prescaler for RF PLL frequency synthesizers using a standard 0.5 /spl mu/m CMOS process and 3.3 V supply. The divide-by 64/65 dual-modulus prescaler has a maximum operating frequency of 1.6 GHz and dissipates 9 mW. The VCO is a single-stage ring oscillator with a maximum frequency of 2.2 GHz and consumes 20 mW. The VCO and prescaler combination operates at a maximum frequency of 1.6 GHz and consumes 56 mW.

Microstrip patch antenna using silicon micromachining technology

The design of a 20 GHz rectangular microstrip patch antenna over micromachinated silicon substrate has been performed using HFSS/spl reg/. The micromachining technique has been used to synthesize a low dielectric constant region in the silicon substrate. In this technique, silicon is partially removed underneath the patch antenna, forming a mixed air-silicon region is controlled to synthesize a predetermined value. The microstrip patch antenna over the micromachined silicon substrate shows better bandwidth with respect to that over Duroid substrate. An improvement of 40% in bandwidth is obtained for an 80% silicon removal. The effect of silicon conductivity has been studied and it has been showed that silicon conductivity enhances the antenna bandwidth at the expense of reduced efficiency.

STUDY OF INTERFACE TRAP PROPERTIES IN MOSFETS USING SPLIT-CURRENT MEASUREMENTS

Abstract A novel experimental method for interface trap characterization in MOSFETs is proposed. The method is based on a detailed time domain analysis of the substrate and source/drain currents, called split-currents, and includes the nonsteady state behaviour of the electron and hole emission processes from the interface traps when large triangular signals are applied to the gate. The interface trap density profiles as well as their capture cross sections in a relatively wide region of the silicon band gap are determined and compared to those obtained from the conductance technique adapted recently to be applied on relatively short channel MOSFETs.

Design, implementation and measurement of 26.6 GHz patch antenna using MEMS technology

The paper presents a 26.6 GHz patch antenna using MEMS technology. In this technology, the patch is suspended over a thin dielectric layer (membrane), which is deposited on a high index silicon substrate. In addition, the silicon substrate is fully etched under the patch, creating an air cavity region of very low dielectric constant (/spl epsiv//sub r//spl cong/1). The antenna is directly fed using a microstrip line, and a CPW-microstrip transition is used for probe measurements of the antenna return loss. The design is performed using the 3D electromagnetic simulator HFSS/sup /spl reg//. The measured antenna return loss is -17 dB at 26.6 GHz, and the bandwidth is 4.5%. The antenna has a radiation efficiency of 61.7% and directivity of 7.9 dB. The measured antenna cross-polarization level is less than -20 dB in both the E- and H-planes.

Hierarchical Analog Behavioral Modeling of Artificial Neural Networks

A hierarchical methodology for analog behavioral modeling of the basic building blocks of neural networks is presented using HDL-A.1 This hierarchy is formed of three levels in order to satisfy the different requirements of the CAD tools which may incorporate the models. The presented models include all the nonidealities present in the actual circuit in addition to being flexible and consuming shorter simulation time. This improvement in simulation time is verified through examples at both the circuit and system levels.

Design equations for the on-state capacitance of the RF MEMS shunt switch

A simple methodology is developed to determine the value of MEMS shunt switch on-state capacitance using established design equations for planar transmission lines. Results agreed with the on-state values provided by 3D electrostatic simulator with an error of less than 4%.

Drain current charge pumping: a new technique for interface trap characterization in VLSI MOS transistors

This paper presents a new characterization technique for interface trap properties in MOS transistors. The proposed technique is particularly suited to submicron transistors since its sensitivity is inversely proportional to the square of the transistors channel length. The proposed method is based on a new analytical model for the pulsed drain current in strong inversion. The model relates the pulsed drain current to the classical charge pumping current thus enabling the determination of the interface trap density and time constant in an easy and accurate way. The method is compared to classical charge pumping measurements and very good agreement is found between the two methods.