Hiroomi Nakajima

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFETs was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFETs also operated at higher speed. >

Autonomous refresh of floating body cell (FBC)

Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a BL can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600 muA refresh current for 1 G-bit memory is achieved in 32 nm technology node with 4 ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

A NiSi salicide technology for advanced logic devices

A nickel-silicide (NiSi) technology for deep submicron devices has been developed. It was confirmed that Ni films sputtered on n- and p-single and polysilicon can be changed to mono-silicide (NiSi) stably at low temperature (600 degrees C) over a short period without any agglomeration. The NiSi layer did not absorb boron or arsenic atoms during silicidation, and a high concentration of boron or arsenic was achieved at the silicide/silicon interface, contributing to a low contact resistance. NiSi technology was applied to a dual-gate CMOS structure. Excellent pn junction characteristics and high drivabilities of both the n- and p-MOSFETs were successfully obtained.<<ETX>>

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

Scaling scenario of floating body cell (FBC) suppressing V th variation due to random dopant fluctuation

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

FBC's Potential of 6F 2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBCs spacers can be optimized for making the SSM as large as 8muA at plusmn 4.5sigma without sacrificing the retention time.

Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications

A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC.

A study of nonequilibrium diffusion modeling-applications to rapid thermal annealing and advanced bipolar technologies

A nonequilibrium diffusion model has been developed to study the influence of point defects on dopant redistribution, especially for transient enhanced diffusion. The coupled equations for point defects, substitutional impurities, and impurities/point defect pairs are solved under nonequilibriums condition. Charged species are included and the Poisson equation is solved. The characteristics and domain of validity of this model have been investigated. Indications are suggested to predict the conditions under which a steady-state model can be used. In the case of high-concentration predisposition, enhanced diffusion is observed and concave or exponential profiles are obtained for very short-time diffusion. Applications are presented for oxide diffusion sources. The generality of the model is confirmed by long-time diffusion behavior and by the influence of phosphorus diffusion on the boron buried layer. Anomalous effects observed during RTA steps after ion implantation are also well reproduced by the model. Successful comparisons with experiments are reported for boron and for actual bipolar structures, with coupled arsenic/boron diffusion in a 0.5- mu m BiCMOS process. >

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.