H. Kudo

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes (M-S) models, in order to include the line height dependence of copper grain size, and applied it in the evaluation of the RC delay variability based on the SPICE simulation. In our results, we found that the RC delay variability in the 45nm node technology was relatively small, weakly dependent on the grid size and line height, and almost not affected by the size effect. On the contrary, in the 32 nm technology, the RC delay variability was about 2 times larger than the case ignoring the size effect and reached to the 20% of the average delay time at 3000 grid with 10% of line size fluctuation. In the 32 nm technology, the line height dependence of the RC delay variability was also strong and increased with decreasing line height. The influence of line height dependence of grain size reached about 1/5 or more of the total size effect in the RC delay variability.

Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node

It is a great concern that a so-called full low-k interlayer dielectric (ILD) structure may degrade reliability of Cu wiring due to the poor thermal conductivity of very low-k (VLK) material. An ILD structure we proposed in this work (named hybrid) are made of VLK for the trench level and SiO/sub 2/ for the via level, to meet following two requirements; reducing wiring capacitance and not decreasing thermal conductivity so much. In this work, we have presented integration of dual damascene patterning and Cu metallization for the hybrid structure.

Strategies of RC Delay Reduction in 45 nm BEOL Technology

According to the 45 nm BEOL technology node, we demonstrated that a homogeneous interlayer dielectric with dielectric constant of 2.25 has a substantial advantage in terms of RC delay reduction compared to other potential architectures such as hybrid and tri-level dielectrics. Combination of the homogeneous interlayer dielectric and ultra-thinned barrier metal lowered the RC delay to 86 % compared to that listed in the ITRS 2006 update.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

We successfully encapsulated Cu wiring with an ultra-thin self-forming barrier consisting of MnO and a bi-layer of MnO/Ta. TDDB test showed that the ILDs lifetime increased by a factor of 100 over that of our control sample. The encapsulated Cu wiring increased EM lifetime by a factor of more than 47. For via chains that are vulnerable to thermal stress, the encapsulated Cu wiring showed no SIV failure. The resistance of the encapsulated Cu wiring was 13% lower than that of the control sample. We expect encapsulated Cu wiring to have greater endurance to the electrical and thermal stresses for use in 32-nm nodes and beyond.

Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique

As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Youngs modulus increased by 1.7 times compared with that of thermally cured NCS. We fabricated two-level Cu wirings layers with NCS cured by optimized e-beam cure technique. The e-beam cure dramatically enhanced the lifetime of time-dependent dielectric breakdown (TDDB) of interlayer dielectrics. We also examined the influence of the charge damage to the MOSFETs under e-beam cured NCS layer and confirmed that there was no e-beam charge damage to the Ion-Ioff characteristics and reliability of MOSFETs with the optimized e-beam cure.

Enhancing Yield and Reliability by Applying Dry Organic Acid Vapor Cleaning to Copper Contact Via-Bottom for 32-nm Nodes and Beyond

Via cleaning using gas-phase organic acid has a high potential for improving the reduction capability of copper oxides (CuO), not degrading porous ultra-low-k dielectrics, and reducing processing cost. We applied our via cleaning technique to intermediate and semi-global levels consisting of homogeneous interlayer dielectric architectures based on the 45-nm technology node. The CuO reduction rate was by a factor of 10, which was much higher compared with that using hydrogen. This allowed us to achieve a 100% yield for a mega-scaled via chain. Via chains treated with gas-phase organic acid also showed greater resistance against stress-induced voiding. In addition, we substantially reduced the via cleaning process cost by a factor of 10 compared with the cost of conventional wet chemical cleaning. In addition, organic acid is preferable because it occurs naturally and is thus ecologically friendly.

Novel low-k SiOC (k=2.4) with superior tolerance to direct polish and ashing for advanced BEOL integration

We established novel SiOC (k=2.4) with higher process damage tolerance. The SiOC was deposited using organo-silane with acetylene bond as a precursor of plasma enhanced chemical vapor deposition (PECVD). The precursor takes high concentration of carbon in the SiOC and the SiOC has closed pores since deposited without using any porogens, therefore lower damage by ashing and direct Cu polish are achieved. We fabricated Cu wirings using direct polish. We confirmed that dielectric constant of the SiOC did not increase after ashing and direct polish process and maintained k=2.4.

Copper wiring encapsulation at semi-global level to enhance wiring and dielectric reliabilities for next-generation technology nodes

The semi-global level is rather different from the intermediate level in terms of wiring scale and types of interlayer dielectrics, which has an impact on the encapsulation capability of MnO. The difference in both levels, therefore, requires major changes of the processes such as the deposition conditions of CuMn seed and capping film. We successfully enhanced wiring and dielectric reliability at the semi-global level as well as at the intermediate level in 45-nm-node technology. For electromigration and dielectric stability, MnO segregated along the outline of the Cu wiring increases activation energy and voltage acceleration factor by 54 and 47%, respectively. These increases effectively enhance the maximum current density and the expected interlayer dielectric lifetime by factors of 28 and 70, compared to those of a control sample.