Masaki Haneda

Ultrathin Barrier Formation Using Combination of Manganese Oxide Encapsulation and Self-Aligned Copper Silicon Nitride Barriers for Copper Wiring in Future LSI Interconnects

Combining Mn oxide/Ta encapsulation and a self-aligned CuSiN barrier enhanced reliability of both wiring and dielectrics, reducing wiring resistance by 10%, compared with that of a control sample. The CuSiN barrier effectively concentrated Mn, resulting in a composite barrier consisting of Mn oxide, Mn silicate, and MnSiN forming on top of the Cu wiring. Mn concentration is attributed to the large difference in the standard heat of formation between Mn silicide and Cu silicide. The composite barrier that formed on top of the Cu wiring played a critical role in enhancing the reliabilities by suppressing surface Cu self-diffusion, vacancy diffusion, and Cu ion drift under electrical and thermal stresses. Suppressing the surface self-diffusion, for example, increased electromigration lifetime by a factor of 51. This combination technique has an advantage over a previous self-formation of a Mn oxide barrier in terms of reliabilities since the previous technique cannot form such a composite barrier on top of the Cu wiring.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

We successfully encapsulated Cu wiring with an ultra-thin self-forming barrier consisting of MnO and a bi-layer of MnO/Ta. TDDB test showed that the ILDs lifetime increased by a factor of 100 over that of our control sample. The encapsulated Cu wiring increased EM lifetime by a factor of more than 47. For via chains that are vulnerable to thermal stress, the encapsulated Cu wiring showed no SIV failure. The resistance of the encapsulated Cu wiring was 13% lower than that of the control sample. We expect encapsulated Cu wiring to have greater endurance to the electrical and thermal stresses for use in 32-nm nodes and beyond.

Restraint of Copper Oxidation Using Barrier Restoration Technique with Cu–Mn Alloy

This paper clarifies for the first time that employing Cu–Mn alloy can reduce the resistance of ultralarge scale integration (ULSI) interconnects. It is well known that Cu alloys have higher resistance than pure Cu. However, recent discussion indicates that Cu or barrier metal oxidation by moisture from interlayer dielectrics causes electrical resistance to increase even further. Therefore, Cu oxidation must be prevented. Previously, we have reported a barrier restoration technique using Cu–Mn alloy, and the application of this technique is expected to result in strong tolerance to Cu oxidation. In this work, we investigated the property that copper is protected from oxidation when using the barrier restoration technique with Cu–Mn alloy. This property results in the reduction of interconnect resistance and the improvement of the resistance distribution in ULSI interconnects. We conclude that using the barrier restoration technique with Cu–Mn alloy will be being compatible with further scaling to 22 nm node and beyond.

Copper wiring encapsulation at semi-global level to enhance wiring and dielectric reliabilities for next-generation technology nodes

The semi-global level is rather different from the intermediate level in terms of wiring scale and types of interlayer dielectrics, which has an impact on the encapsulation capability of MnO. The difference in both levels, therefore, requires major changes of the processes such as the deposition conditions of CuMn seed and capping film. We successfully enhanced wiring and dielectric reliability at the semi-global level as well as at the intermediate level in 45-nm-node technology. For electromigration and dielectric stability, MnO segregated along the outline of the Cu wiring increases activation energy and voltage acceleration factor by 54 and 47%, respectively. These increases effectively enhance the maximum current density and the expected interlayer dielectric lifetime by factors of 28 and 70, compared to those of a control sample.