H.Kusuki

Numerical simulation of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current is reduced due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e. it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer. >

Simplified simulations of GaAs MESFET's with semi-insulating substrate compensated by deep levels

Current-voltage characteristics of GaAs MESFETs (with p-butter layers) on semi-insulating substrates compensated by deep levels are simulated by two-carrier and one-carrier models. For a thicker p-buffer layer or for higher acceptor density in the substrate, the drain current becomes lower because the substrate current is reduced. The one-carrier model also gives reasonable results for a case with a hole-trap substrate. Small-signal parameters of GaAs MESFETs on various types of substrates are also simulated. For a thicker p-buffer layer or for higher acceptor densities in the semi-insulating substrates, the substrate current is reduced, and both transconductance and cutoff frequency become higher. It is concluded that, to utilize the high-speed and high-frequency performance of GaAs MESFETs, acceptor densities in the substrate should be made high. >

Effects of impact ionization on I-V characteristics of GaAs n-i-n structures including hole trap

Numerical simulations of GaAs n-i-n structures with Cr deep acceptors (hole trap) in the i-layer are performed by considering the impact ionization of carriers. At low voltages, I-V curves show sublinear or saturated features, because the voltage is entirely applied along the reverse-biased n-i junction. When the deep-acceptor density is low, a steep rise of current occurs due to trap filling, whereas when the deep-acceptor density becomes high, the steep current rise occurs due to impact ionization of carriers at the reverse-biased n-i junction. In this case, the voltage for current rise becomes lower as the acceptor density becomes higher.<<ETX>>