H. McLelland

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.

Scaling of Hydrogen-Terminated Diamond FETs to Sub-100-nm Gate Dimensions

We present the dc operation of hydrogen-terminated diamond field-effect transistors (FETs) with gate lengths of 1 μm to 50 nm. The 50-nm device metrics include a maximum drain current of 290 mA/mm and a peak extrinsic transconductance of 95 mS/mm. As the device gate length is reduced, peak intrinsic transconductance is increased substantially to a value of 650 mS/mm for the 50-nm device. A minimum Ion/Ioff ratio of ~ 1.5 × 104 is maintained at this reduced gate dimension. These results appear highly promising for the improvement of hydrogen-terminated diamond FET high-frequency performance through reduction of the device gate length to sub-100-nm dimensions.

Fabrication of ultrashort T gates using a PMMA/LOR/UVIII resist stack

In this article, we report a procedure for the fabrication of ultrashort T gates using high resolution electron beam lithography and a PMMA/LOR/UVIII resist stack. The intermediate lift-off resist (LOR) layer improves the quality of gate lithography, and consequently, device yields. It is unaffected by wet chemical gate recessing procedures and we report the application of the procedure to the fabrication of pseudomorphic and metamorphic high electron mobility transistors (pHEMTs) with 50 nm T gates. Fabricated pHEMTs had a gm of 600 mS/mm and ft of 200 GHz. Metamorphic HEMTs had a gm of 1500 mS/mm and ft of 350 GHz. We believe these are the fastest transistors of their kind in the world.

Metal gate strained silicon MOSFETs for microwave integrated circuits

In this work a III-V MODFET fabrication process has been adapted to fabricate metal gate silicon based MOSFETs. A range of MOSFETs with gate lengths varying from 1 /spl mu/m to 120 nm were fabricated and all showed good transistor action. The gate metal was Ti/Pd/Au 200 nm thick and both pyramidal and T shaped gates were fabricated. The parasitic gate-source capacitance was reduced by using a spin on dielectric. The strained silicon MOSFETs with rectangular 0.3 /spl mu/m Ti/Pd/Au gates had measured f/sub T/ and f/sub max/, of 11 GHz and 12 GHz respectively. By de-embedding the parasitic pad capacitance the intrinsic f/sub T/ and f/sub max/ are 20 GHz and 21 GHz.

Novel technologies for the realisation of GaAs pHEMTs with 120 nm self-aligned and nanoimprinted T-gates

To address the major issues of increasing device frequency performance and reducing fabrication costs of 100 nm scale gate length III-V HEMT devices, two novel technologies developed for GaAs pHEMT are reported, namely: (i) A low resistance, non-annealed Ohmic contact technology based on a thin metallisation and highly doped In0.2GaAs/GaAs cap layer which is compatible with a self-aligned gate process. (ii) A succinic acid based gate recess etch which selectively etches the In0.2GaAs/GaAs cap required for the non-annealed ohmic contact technology, stopping on a 5-nm Al0.3GaAs etch stop layer. Incorporating both of these processes, self-aligned T-gate and nanoimprinted T-gate devices have been realised. Completed self-aligned T-gate GaAs pHEMT devices of 120 nm gate length exhibited an fT and fmax of 135 and 180 GHz, respectively, while nanoimprint 120 nm GaAs pHEMT devices demonstrated excellent DC characteristics, including a transconductance of 450 mS/mm.

50nm GaAs mHEMTs and MMICs for Ultra-Low Power Distributed Sensor Network Applications

We report well-scaled 50 nm GaAs metamorphic HEMTs (mHEMTs) with DC power consumption in the range 1-150 muW/mu demonstrating fT of 30-400 GHz. These metrics enable the realisation of ultra-low power (<500 muW) radio transceivers for autonomous distributed sensor network applications

Low noise high performance 50nm T-gate metamorphic HEMT with cut-off frequency f/sub T/ of 440 GHz for millimeterwave imaging receivers applications

The 50 nm m-HEMT exhibits extremely high f/sub T/, of 440GHz, low F/sub min/ of 0.7 dB, associated gain of 13 dB at 26 GHz with an exceptionally high Id of 200 mA/mm and gm of 950 ms/mm at low noise biased point.

Low noise W-band MMMIC amplifier using 50nm InP technology for millimeterwave receivers applications

We report on W-band LNA (MMMICs) based around a 50nm InP-HEMTs with an fT of 0.550 THz. The LNA noise figure is 2.5 dB and associated gain of 7.3 dB at 90 GHz with a bandwidth of 24 GHz

A high performance, high yield, dry-etched, pseudomorphic HEMT for W-band use

A GaAs pseudomorphic HEMT process has been optimised for high performance and yield at W-band. Several key nano-fabrication techniques are explored for performance, manufacturability and process sensitivity. The molecular beam epitaxially grown pHEMT layer is optimised for reduced short channel effects, high transconductance (690 mS/mm) and reliability. Electron-beam lithography produces ultra short T-gates with high reproducibility. Selective reactive ion etching enables both the depth and width of the gate recess to be accurately controlled. 0.2 /spl mu/m pHEMTs with two 50 /spl mu/m gate fingers exhibit average values for f/sub T/ and f/sub max/ of 121 and 157 GHz with low standard deviations of 4.6 and 2.9 GHz respectively.<<ETX>>

Effects of pressure and capping layer thickness on sub-micron T-gate recess etching of GaAs p-HEMTs by SiCl4/SiF4/O2 reactive ion etch

Reactive ion etching for T-gate recessing has a vital importance in the fabrication of high performance sub-micron gate length GaAs pseudomorphic high electron mobility transistors (pHEMTs), because the geometry after etching significantly affects the device performance. In this work, the impact of etching parameters on the recess geometry has been investigated for various cap layer thicknesses in the range 20–50 nm by using SiCl4/SiF4/O2 chemistry in a RIE system. It was found that the etching pressure plays a significant role in defining the recess geometry. A pressure of 100 mTorr and etch time of less than 1 min, with a gas flow of SiCl4/SiF4/O2=1.2:8.2:0.15 (sccm) and a RF power of 18 W are required to ensure controllable and repeatable recess geometries (both vertical and lateral) for layer structures with GaAs cap thickness of less than 30 nm. In contrast, a pressure of 250 mTorr and etch time of 2 to 2.4 min are required to uniformly etch devices with cap thickness of greater than 30 nm without serious resist erosion. pHEMTs with 0.12 μm gate length made using this dry etching process showed very good electrical performance.