H. Speek

Defect-oriented testing of Josephson logic circuits and systems

In this paper, defect-oriented testing of low temperature superconducting Josephson logic systems is used as a basis for structural test generation. This requires the investigation of processing defects using defect monitors and the development of fault models. Inductive fault analysis techniques play an important role in this approach. By means of fault injection in the JSIM circuit simulator, the most effective test signals can be derived which can subsequently be used for test-generator hardware in a built-in self test environment.

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.

Bridging the testing speed gap: design for delay testability

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed.

MISMATCH: a basis for semi-automatic functional mixed-signal test-pattern generation

This paper describes a tool which assists the designer in the rapid generation of functional tests for mixed-signal circuits down to the actual test-signals for the tester. The tool is based on manipulating design data, making use of macro-based test libraries and tester resources provided by the test engineer, and computer-based interaction with the designer.

Design for Delay Testability in High-Speed Digital ICs

The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed.

Boundary-scan Testing for Mixed-Signal MCMs

A multi-chip module implementation is shown which provides new features and conditions for mixed-signal boundary-scan testing of MCMs. Assembled non boundary-scan mixed-signal bare dies and integrated passive devices can be tested using active-substrate MT circuits. The MCM-D is very well suited for electron-beam diagnosis.

Mixed-Signal Testing at the ASIC Design Course at Twente University

At our faculty the students have to follow an extensive (mixed-signal) ASIC design course in the third year of the program. In [1] we have presented an overview of the whole course, but in the meanwhile we have extended the mixed-signal test part of this ASIC design course considerably. In our course the students have to design and test a so-called dial-memo IC (see Figure 1).

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.

The Mixed-Signal ASIC Design Course at Twente

In this paper we give a detailed overview of the ASIC design course as it is being given at the Department of Electrical Engineering of the University of Twente. This course covers the complete trajectory from system design via circuit design and actual implementation to testing. Design and testing are not limited to the digital field only, but contain also a substantial analogue and mixed-signal part.