H.T. Weaver

An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively--primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM.

Mechanisms Leading to Single Event Upset

SRAM cell recovery time following a 140 MeV Krypton strike on a Sandia SRAM is modelled using a two-dimensional transient numerical simulator and circuit code. Strikes at both n- and p-channel off drains are investigated. Four principle results are obtained. The recovery time after a strike is strongly dependent on the drive of the restoring transistor. A struck off p-channel drain-to-gate capacitive coupling has a significant effect on recovery in SRAM with feedback resistors. Recovery time is approximately linear with LET over LET in the range to 0.4 pC/¿. Finally, an experimental n-channel SEU has been observed in a Sandia SRAM without feedback resistors.

Memory SEU simulations using 2-D transport calculations

An advance in the simulation of a single event upset (SEU) of a static memory is achieved by combining transport and circuit effects in a single calculation. The program SIFCOD [4] is applied to the four transistors of a CMOS SRAM cell to determine its transient circuit response following a very high energy ion hit. Results unique to this type of calculation include determination of relative upset sensitivites and different upset mechanisms for specific area hits, i.e., the OFF p-channel drain, the OFF or ON n-channel drain, etc. The calculation determines the transport variables as a function of time in two-space dimensions for each of the four transistors and provides the nodal voltage and current responses for assessing memory upset conditions.

A proposed new structure for SEU immunity in SRAM employing drain resistance

A novel static random access memory (SRAM) cell is proposed (LRAM) in which resistors are used to delay ion-induced transients conventionally, and to divide down voltage transients at the information node. The voltage divider is a new concept in SEU hardening and has practical value for technologies where the voltage transient duration is significantly different for responses to ion strikes at p- and n-channel drains. In combination, the two pairs of resistors allow much reduced resistor values with the advantage of faster access times, better temperature stability, and better scalability. Advanced simulations in which transport and circuit effects are modeled simultaneously are used to project the viability of the LRAM concept and data from single-cell test structures and support the analysis.

Comparison of 2D Memory SEU Transport Simulation with Experiments

Single event upset (SEU) simulations in SRAM cells have been carried out and the results are compared to experimental data on 16K bit memories. The simulations consisted of simultaneous calculations of charge transport and transient circuit response for four cross-coupled CMOS transistors following the introduction of a slab of excess carriers into the off p-channel drain. The experiments collected upset rates produced in the memories by 163 MeV argon ions directed normally to the chip surface. Agreement between experiment and calculation was achieved when (1) the p-channel transistors were integrated into a single block of silicon as in the memory cell layout and (2) scaling was done on the Auger coefficients to compensate for an inherent 2D effect.

Two-Dimensional Simulation of Single Event Indujced Bipolar Current in CMOS Structures

Single particle effects are analyzed using an advanced two-dimensional transient numerical simulator. Layered structures representative of an n-channel MOSFET drain in a p-well are modeled. TWo major results have been obtained. First, the well structure inherently provides better charge collection at the well-substrate compared to the drain-well junction. Ihis provides single event protection for the drain node. Second, large charge density tracks generated by very high energy particles can forward bias the drain-well junction resulting in bipolar action from the inherent parasitic n-p-n transistor of the well structure. This bipolar current is opposite to the photocurrent, suggesting a different SEU protection mechanism. However, it opens the possibility of upset of the on n-channel and, most critically, provides a mechanism for triggering latch-up in CMOS circuits.

Soft error stability of p-well versus n-well CMOS latches derived from 2-D transient simulations

Numerical simulations for the response of inverters to high-energy ion strikes are used to compare the single-event-upset (SEU) hardness of p- versus n-well technologies. A constant-geometry, mirror-image technique is used to generate the technology designs, with the objective of presenting features inherent to the well type. The p-well exhibits better SEU tolerance at low ion energies, but in the high-energy regime the two technologies become essentially equivalent. This results from saturation effects known to occur in modern SRAMs (static random access memories).<<ETX>>

Radiation-Tolerant, Sidewall-Hardened SOI/MOS Transistors

Total dose radiation effects were measured for sidewall-hardened n-channel SOI/MOS transistors, fabricated in zone-melt-recrystallized (ZMR) and oxygen-implanted (SIMOX) SOI materials. We compare the radiation responses of transistors with three types of sidewall or edge configurations: island transistors with passivated edges, island transistors without passivated edges, and edgeless (enclosed-gate) transistors. Data from these three test devices allow clear separation of front-, back-, and edge-channel conduction. Passivated edge channels were hard to Co-60 doses in excess of 24 Mrad(Si). The overall hardness of the passivated-edge transistors is limited only by the radiation-induced threshold voltage shifts (about -1 V at 1.0 Mrad) of the top channel. No significant differences in total-dose response of ZMR and SIMOX devices were observed under the radiation conditions employed.

RAM cell recovery mechanisms following high-energy ion strikes

Recovery times for a RAM cell following a high-energy ion strike are calculated using simulation techniques in which transport and circuit behavior are modeled simultaneously. The recovery time, typically several nanoseconds for a 140-MeV Kr strike, is intermediate to analytical results for funneling and diffusion. For such large strikes, the primary factor determining recovery is modulation of the photocollection by loading at the struck node, not intrinsic funneling characteristics, as is expected for smaller alpha particle strikes. The recovery is fundamentally linked to the cell configuration and cannot be accurately modeled using calculations representative of the individual cell elements.

Soft error protection using asymmetric response latches

A static latch design is analyzed whose single event upset (SEU) sensitivity is extremely dependent on its logic state. The authors employ a modification of a hardened static memory cell to construct an asymmetrical latch. Both the original and asymmetric latches are illustrated. The original idea was that resistors in the drain lines provide voltage division at the feedback point for p-drain strikes (or voltage transients). Proper choice of the resistor value relative to the on resistance of the n-channel transistor will insure that the feedback voltage can never reach the switch point of the opposite inverter, preventing cell upset for any p-drain transient. Such latches respond symmetrically with respect to logic state, displaying essential immunity to one SEU mechanism. A simple AND gate for two of these asymmetric response latches provides high-speed error correction for a single bit, and the combination represents a hardened logic element. >