J.S. Fu

An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively--primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM.

Memory SEU simulations using 2-D transport calculations

An advance in the simulation of a single event upset (SEU) of a static memory is achieved by combining transport and circuit effects in a single calculation. The program SIFCOD [4] is applied to the four transistors of a CMOS SRAM cell to determine its transient circuit response following a very high energy ion hit. Results unique to this type of calculation include determination of relative upset sensitivites and different upset mechanisms for specific area hits, i.e., the OFF p-channel drain, the OFF or ON n-channel drain, etc. The calculation determines the transport variables as a function of time in two-space dimensions for each of the four transistors and provides the nodal voltage and current responses for assessing memory upset conditions.

SEU characterization of a hardened CMOS 64K and 256K SRAM

The first single-event-upset (SEU) tests of the AT&T 64K and 256K SRAMs (static random-access memories) have been performed. Feedback resistor values for these parts ranged from 200 k Omega to 1 M Omega . All were fabricated using the 1- mu m, 2-level-poly, 2-level-metal process. Ions used for the tests were Ar, Cu, Kr, and Xe, providing a range of effective LET (linear energy transfer) values from 20 to 129 MeV-cm/sup 2//mg. With the 64K SRAM operating at 4.5 V and 90 degrees C, an upset threshold LET of 30 MeV-cm/sup 2//mg and saturation cross section of 1.5*10/sup -2/ cm/sup 2/ were measured with a nominal room-temperature feedback resistance of 450 k Omega . In Adams 10% worst-case environment using the Petersen approximation (see E.L. Petersen et al., ibid., vol.NS-30, p.4533-9, Dec. 1983) this implies an error rate of 1.3*10/sup -7/ errors per bit-day. With a nominal 650-k Omega feedback resistance, a 256K SRAM had a calculated error rate of about 3*10/sup -8/ errors power bit-day at 4.5 V and 90 degrees C. These data agree well with earlier data for a 1 kb test chip. The minimal feedback resistance required to prevent upset versus LET is calculated, using an activation energy of 0.10 eV to estimate the decrease in feedback resistor value as a function of temperature. >

A proposed new structure for SEU immunity in SRAM employing drain resistance

A novel static random access memory (SRAM) cell is proposed (LRAM) in which resistors are used to delay ion-induced transients conventionally, and to divide down voltage transients at the information node. The voltage divider is a new concept in SEU hardening and has practical value for technologies where the voltage transient duration is significantly different for responses to ion strikes at p- and n-channel drains. In combination, the two pairs of resistors allow much reduced resistor values with the advantage of faster access times, better temperature stability, and better scalability. Advanced simulations in which transport and circuit effects are modeled simultaneously are used to project the viability of the LRAM concept and data from single-cell test structures and support the analysis.

RAM cell recovery mechanisms following high-energy ion strikes

Recovery times for a RAM cell following a high-energy ion strike are calculated using simulation techniques in which transport and circuit behavior are modeled simultaneously. The recovery time, typically several nanoseconds for a 140-MeV Kr strike, is intermediate to analytical results for funneling and diffusion. For such large strikes, the primary factor determining recovery is modulation of the photocollection by loading at the struck node, not intrinsic funneling characteristics, as is expected for smaller alpha particle strikes. The recovery is fundamentally linked to the cell configuration and cannot be accurately modeled using calculations representative of the individual cell elements.

Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K

The processing and design geometric scaling effects on the soft-error tolerance levels of the 16K 2-µm technology and the 256K 1-µm technology CMOS SRAMs are separated by fabricating the 16K 2-µm design with the 1-µm process. Although the 1-µm twin-tub process is inherently more tolerant than the p-well process to soft errors, the densely packed 1-µm memory cells become very soft because of the dominant effect of the channel width reduction. An advanced device-plus-circuit simulator was used to calculate the differential contribution from each of the vertical and lateral dimensional changes involved in the technology transition. Good agreement between the simulations and the experimental data is reached by properly correcting the 2D model to account for the phenomenal saturation effect involving very heavy ions.

Processing Enhanced SEU Tolerance in High Density SRAMs

We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandias 2¿m-technology 16K SRAMs are fabricated with a radiation-hardened 1-¿m CMOS process. An advanced 2D transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the 2-¿m process to the 1-¿m process. Error cross-section data, performed at the Berkeley cyclotron, on the first such device lot indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with the high-LET events is described and physical mechanisms responsible for the saturation are discussed.

A direct SRAM soft-error cross-section simulation with two-dimensional transport calculations

An advance in the simulation methodology for memory circuit soft-error is accomplished by simultaneous calculation of transient charge transport and circuit response for the four cross-coupled CMOS transistors of a SRAM cell following a severe carrier density perturbation. By comparing the critical circuit voltage required for error immunity directly with the experiments, we circumvented limitations imposed by 2D approximation and uncovered upset mechanisms, which, if exploited, will lead to stabilization against upset. For voltages less than this critical value, we find spatial dependence for upset sensitivities, even within the same drain diffusions, from which the dependence of upset cross section on circuit supply voltage may be assessed.