Hisato Oyamatsu

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFETs in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch.

4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure

For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<<ETX>>

Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET

A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n/sup /spl minus// design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n/sup /spl minus// extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n/sup /spl minus// extension region. Furthermore, it was also confirmed that the 0.3 /spl mu/m optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance. >

Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <1.2 nm.

High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.

Compact model for layout dependent variability

We have developed a compact model which deals with MOSFET characteristic variations arising from design layout dependences. It treats many stress related variations and their interactions that are especially important in 45 nm technology node. It is demonstrated that the model can predict MOSFET characteristics used in standard cells with high accuracy.

A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

A high performance 0.3 /spl mu/m CMOS technology has been developed for high speed logic LSIs. A new gate formation technology achieved 0.3 /spl mu/m gate length MOSFETs by i-line based lithography and new ARC process. An optimized PLDD nMOSFET and buried channel pMOSFET achieved high current drivability without spoiling their reliability in 3.3 V operation. Moreover, ion implantation restricted only for channel/isolation region and SiOF low interlayer dielectric process reduced junction capacitance and wiring capacitance, respectively. Furthermore, CMP planarization process and selective CVD-W filling for contacts/vias achieved borderless design with the improvement of device density. The 0.3 /spl mu/m CMOS technology has performed 1.2 times improvement from conventional 0.35 /spl mu/m CMOS technology in a typical critical path of advanced MPUs.

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel junctions (MTJ) required switching current, there have also been reports on high-capacity (up to tens of Mb) STT-MRAM [1–4]. In [2] a perpendicular-TMR (pMTJ) device is used to reduce the switching current and a high-speed current sense amplifier is proposed. In [3] a 54nm 2T-1MTJ 14F2-cell is proposed that uses a high-density DRAM process: self-aligned contact and plug process. However, the unit cell area of STT-MRAM is still much larger than that of DRAM, making STT-MRAM not cost-competitive to contemporary DRAM.