Tetsuya Asami

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

A 1Mb virtually SRAM

Suppressed VLSI with Submicron Geometry”, ISSCC DIGEST ’Sakurai, T., Kakumu, M . and Iizuka, T., “Hot-Carrier O F T E C H N I C A L P A P E R S , p. 272-273; Feb., 1985. “HotJ S S C ; to he published. Carrier Generation in Submicron VLSI Environment”, IEEE Insertion (NOEMI) technology5 is applied selectively to bootstraped nodes to endow hot-carrier resistancy to the circuits. N-channel memory cells are embedded in a P-well for protection from the minority carrier injection from I/O pins and alpha-particle induced electrons. Yo substrate bias is applied to reduce the standby current. Process related parameters are listed in Table 1. A double-level poly-Si and double level A1 process has been employed for circuit speed. The cell capacitor is planar and the design rule is 1.2pm. A microphotograph of the chip is shown in Figure 4. Figure 5 demonstrates a typical address access time of 62ns. The slower access is the worst case access time; Le., refresh operation taking place in advance of the normal access. The faster access is without refresh. This measurement is carried out by a test enable pin that affords control of the refresh-request signal externally. Since the access time without refresh is 48ns, the access time overhead by the background refresh is 29%. Electron beam tested internal waveforms are also shown in Figure 5. Quick switch from refresh to normal operation can be achieved by the dual bootstrap system, where one system is precharged when the other one is in operation. The pin configuration is shown in Figure 6. SRAMs. The SRAM is believed to be a promising substitute for large-capacity Acknowledgments The authors wish to thank S. Fujii, S. Saito, K. Natori, T. Ohtani, K. Taniguchi, Y. Nishi and K. Shimuzu for encouragement and discussions. Theyalso thank Y. Ito, K. Sat0 and K. Matsuda for support. Technology Twin well CMOS Layers Double poly-Si and double A1 Gate length l .op(NMOS), 1.2puPMOS) Junction depth 0.20,u(N+), 0.35p(Pt) Cap. oxide thickness l0nm Gate oxide thickn ss 20nm Poly-Si (WidthlSpace) 1.0pm / 1.4pm 1 s t AI (WidthlSpace) 1.3pm / 1.5pm Contact hole 1.lpm / 1.4pm 2nd Al (WidthlSpace) 1.8pm / 1.9pm Via hole 1.8pm / 2.0pm TABLE 1-Process parameters.

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs. >

Advanced yield enhancement methodology for SoCs

A yield simulator utilizing the extracted critical area and a SoC yield management system has been developed. This system drastically improved accuracy of SoC yield prediction and successfully extracted the critical areas of all layers of 0.18 /spl mu/m SoCs in approximately one hour. For yield prediction, we have thus far extracted critical areas of over 150 SoCs since the 0.18 /spl mu/m nodes, and performed analysis of yield-loss factors. There are two factors that affect the device yield: field defects and product-inherent parametric failure. The yield calculated on the basis of critical areas is a prediction derived considering only field defects. It has been confirmed that SoCs failed to achieve the prediction had product-inherent parametric problems. The new system allows us to determine early in the development cycle whether or not a SoC has any inherent problems. The new system helps to quickly identify the root cause of a yield loss and reduce the time required to obtain yield improvement. Based on the experience of analyzing many SoC products, we have acquired design-for-manufacturing (DFM) expertise for improving yields for new and next-generation products.

Suppression of NBTI-induced VMIN shifts using hafnium doping to gate poly/SiON interface and optimized NiPt process for 40nm node SRAM cell

Hafnium introduction to poly/SiON interface has been found effective to suppress the increase of minimum operating voltage (VMIN) caused by NBTI-induced VT shift in 40nm node low power SRAM. In addition, the distribution tail of N+ node junction leakage current has been identified as enhancing VMIN failure due to NBTI, and has been improved by optimizing NiPt silicide process. Finally operation of 32Mbit 0.24µm2 low power SRAM with VMIN less than 0.9V has been demonstrated.