Hadong Jin

A 34% PAE, 26-dBm output power envelope-tracking CMOS power amplifier for 10-MHz BW LTE applications

An envelope tracking CMOS power amplifier is implemented in 0.18-µm CMOS, and achieves a PAE of 34%, an EVM of 3.2%, and an ACLR of −32.5 dBc at an average output power of 26 dBm and a frequency of 1.8 GHz for a 10-MHz BW 16 QAM 7.5-dB PAPR LTE signal. The envelope tracking operation improves a PAE by 2% to 6.5% over the stand-alone PA for the LTE signal.

9.5 efficient digital quadrature transmitter based on IQ cell sharing

As new complex communication standards employ various modulation methods in various frequency bands, interest in the software-defined radio (SDR) transceiver to support the standards is increasing. For the flexible transceiver, a digital-intensive transmitter has many advantages and has been pursued intensively. The efficiency of the transmitter chain is strongly dependent on the PA, and switching PAs, such as Class-D and F PAs, are used due to their high efficiency. A polar transmitter is suited for the switching operation and receives a large attention. However, a CORDIC is needed for l/Q-to-Polar conversion, and it is very complex. Moreover, the polar signal has a large bandwidth compared to the l/Q signal bandwidth. On the contrary, the quadrature transmitter that does not require the CORDIC, is simple and low computing cost with low power consumption. Due to the favorable characteristics, the quadrature transmitters have been studied. [1] employs an RFDAC based on a Gilbert mixer. It operates in a current mode and the output impedance varies with the number of on-cells. Due to the impedance variation, it is difficult to have a high linearity. In [2], the input digital code is processed by delta-sigma modulation for smaller digital bits and enhanced resolution. However the modulator generates quantization noise. In [3-6], a voltage-mode transmitter is employed with a power combiner based on a switched capacitor. The output impedance is constant, determined by the total capacitance regardless of the on/off cell condition. Moreover, this architecture delivers much higher output power and efficiency than previously reported works. [4] used delta-sigma modulation with cascade PWM to improve linearity. In [5], a quadrature architecture was employed to eliminate the problems of the polar architecture. Due to the 90° phase difference of conventional digital l/Q LOs, the output power of the conventional quadrature transmitter has lower than that of polar, maximum 3dB lower when the magnitude of I and Q are equal.

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18- μm RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance.

Enhanced linearity of CMOS power amplifier using adaptive common gate bias control

This paper presents a fully-integrated linear CMOS power amplifier (PA) with an adaptive gate bias circuit in Common-Gate (CG) amplifiers. The bias circuit is proposed to achieve a high linearity with deep class-AB biasing of Common-Source (CS) stage. The proposed single stage PA including the bias circuit is fabricated using 0.18-μm RF CMOS technology. The adaptive gate bias circuit improves the evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) about 7 dB at a mid power region and 2.5 dB at a high power over a constant bias for the same LTE signal.

Highly efficient and wideband digital quadrature transmitter

A digital quadrature transmitter employing RF DACs, with an array of class-D PA and a distributed capacitor power combiner, directly generates RF signal from digital I and Q signals. Employing a disable opposite cell technique on this RF DAC enables good performances. The measured drain efficiencies and total efficiencies of the implemented transmitter are 14.4/11.0/10.6% and 10.8/6.7/6.3% at peak output power of 7.87/0.26/-0.11 dBm for CW/LTE 5-MHz/LTE 10-MHz signals, respectively.

Dynamic feedback and biasing for a linear CMOS power amplifier with envelope tracking

This paper presents a fully integrated CMOS power amplifier (PA) with a dynamic feedback and gate biasing. The two dynamic circuits improve the linearity and efficiency of the stand-alone PA and ET PA. The proposed CMOS ET PA including the dynamic control circuits is fabricated using 0.18-μm CMOS process. For a long-term evolution (LTE) signal at 1.85 GHz with a 10-MHz bandwidth and a 16-QAM 7.5 dB PAPR, the CMOS envelope tracking (ET) PA module achieves a power-added efficiency (PAE) of 35.4%, an error vector magnitude (EVM) of 3.6%, and an ACLRE-UTRA of -33.3 dBc at an average output power of 26.5 dBm. The ET PA with the control circuits improves the gain deviation within 2 dB and the PAE up to 5%, respectively, according to the output power level, over those of the ET PA without the dynamic control for the same LTE signal.

Development of a highly efficient and linear differential CMOS power amplifier with harmonic control

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with a second harmonic circuit at the common-gate (CG) stage. The proposed single stage PA including the harmonic control circuit is fabricated using 0.18-μm RF CMOS technology with a printed board circuit based output transformer. The impact on the nonlinearity of the common-gate stage is analyzed. The CMOS PA module achieves a power added efficiency (PAE) of 38.7%, an error vector magnitude (EVM) of 5.4%, and the adjacent channel leakage ratio (ACLR) of -30.4 dBc at the average output power of 27.8 dBm and the frequency of 1.85 GHz for the 10-MHz bandwidth (BW) 16-QAM 7.5-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal.

Efficient Digital Quadrature Transmitter Based on IQ Cell Sharing

In this paper, we proposed and designed a digitally configured versatile RF quadrature transmitter. The transmitter efficiency was enhanced by IQ cell sharing and the deactivation of cells of opposite phases. In simulation, these techniques were able to increase the average efficiency of the transmitter from 46.3% to 70.7% for a 6.9-dB PAPR LTE signal. Moreover, the number of power amplifying cells was halved, improving the total efficiency of the transmitter. The proposed transmitter was implemented in a 6-b configuration at 0.8 GHz using a 28-nm CMOS process. Furthermore, the performance of the transmitter was verified. The dynamic range of the measured output power was in the range −20.2 to 13.9 dBm, and the measured average output power was 6.97 dBm for the 6.9-dB PAPR LTE signal. The measured power-added efficiencies of the transmitter at the peak power and average power were 40.43% and 29.1%, respectively.