Sangsu Jin

Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control

Highly linear and efficient CMOS cascode power amplifiers (PAs) are developed for handset applications. The linearity of the PAs is improved using adaptive bias circuits at the gates of the common-source (CS) and the common-gate (CG) stages. The memory effects that are generated by the bias circuits are reduced using second harmonic control circuits at the source of the CS and the gate of the CG stages. The proposed PA, including the integrated bias circuits, is fabricated using a 0.18-μm RF CMOS technology. The adaptive gate bias circuits improve the linearity and efficiency significantly. The measurement results show that the sideband asymmetry is less than 1.5 dB and the peak average power is improved by 1.2 dB within the linearity specification for a 16-QAM 7.5 dB PAPR LTE signal. The bias circuits improve the linearity of the PA within the specification without using digital pre-distortions. The CMOS PA delivers a power-added efficiency (PAE) of 41.0%, an error vector magnitude (EVM) of 4.6%, and an average output power of 27.8 dBm under an ACLRE-UTRA of -31.0 dBc for a 10-MHz bandwidth signal at 1.85-GHz carrier frequency.

A 34% PAE, 26-dBm output power envelope-tracking CMOS power amplifier for 10-MHz BW LTE applications

An envelope tracking CMOS power amplifier is implemented in 0.18-µm CMOS, and achieves a PAE of 34%, an EVM of 3.2%, and an ACLR of −32.5 dBc at an average output power of 26 dBm and a frequency of 1.8 GHz for a 10-MHz BW 16 QAM 7.5-dB PAPR LTE signal. The envelope tracking operation improves a PAE by 2% to 6.5% over the stand-alone PA for the LTE signal.

Control of IMD Asymmetry of CMOS Power Amplifier for Broadband Operation Using Wideband Signal

A fully integrated linear CMOS power amplifier (PA) for the broadband operation is developed for handset applications. This amplifier can handle a wideband signal. To achieve broadband/wideband operation, an analysis of the intermodulation distortion for the asymmetric source in a differential cascode structure is presented. Based on the analysis, the linearization technique using a second harmonic circuit at the gate of the common gate is proposed to reduce the asymmetry. The proposed PA with an on-chip transmission-line transformer, which has a broadband matching characteristic, is fabricated using a 0.18-μm RF CMOS technology. The measurement results show that the sideband asymmetry is less than 0.6 dB for a signal with up to 50-MHz bandwidth, and the peak average power is improved by 1.2 dB within the linearity spec of a 16-QAM 7.5-dB peak-to-average power ratio long-term evolution signal. The PA delivers a power-added efficiency of 36.5%-31.2% and an average output power of 27.5-27.1 dBm under an ACLRE-UTRA of -30.5 dBc for a 50-MHz bandwidth signal across 1.4-2.0-GHz carrier frequency.

9.5 efficient digital quadrature transmitter based on IQ cell sharing

As new complex communication standards employ various modulation methods in various frequency bands, interest in the software-defined radio (SDR) transceiver to support the standards is increasing. For the flexible transceiver, a digital-intensive transmitter has many advantages and has been pursued intensively. The efficiency of the transmitter chain is strongly dependent on the PA, and switching PAs, such as Class-D and F PAs, are used due to their high efficiency. A polar transmitter is suited for the switching operation and receives a large attention. However, a CORDIC is needed for l/Q-to-Polar conversion, and it is very complex. Moreover, the polar signal has a large bandwidth compared to the l/Q signal bandwidth. On the contrary, the quadrature transmitter that does not require the CORDIC, is simple and low computing cost with low power consumption. Due to the favorable characteristics, the quadrature transmitters have been studied. [1] employs an RFDAC based on a Gilbert mixer. It operates in a current mode and the output impedance varies with the number of on-cells. Due to the impedance variation, it is difficult to have a high linearity. In [2], the input digital code is processed by delta-sigma modulation for smaller digital bits and enhanced resolution. However the modulator generates quantization noise. In [3-6], a voltage-mode transmitter is employed with a power combiner based on a switched capacitor. The output impedance is constant, determined by the total capacitance regardless of the on/off cell condition. Moreover, this architecture delivers much higher output power and efficiency than previously reported works. [4] used delta-sigma modulation with cascade PWM to improve linearity. In [5], a quadrature architecture was employed to eliminate the problems of the polar architecture. Due to the 90° phase difference of conventional digital l/Q LOs, the output power of the conventional quadrature transmitter has lower than that of polar, maximum 3dB lower when the magnitude of I and Q are equal.

CMOS Linear Power Amplifier with Envelope Tracking Operation (Invited Paper)

A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 μm RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the 2 nd harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an ACLRE-UTRA of ?32.7 dBc at an average output power of 27 dBm.

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18- μm RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance.

Enhanced linearity of CMOS power amplifier using adaptive common gate bias control

This paper presents a fully-integrated linear CMOS power amplifier (PA) with an adaptive gate bias circuit in Common-Gate (CG) amplifiers. The bias circuit is proposed to achieve a high linearity with deep class-AB biasing of Common-Source (CS) stage. The proposed single stage PA including the bias circuit is fabricated using 0.18-μm RF CMOS technology. The adaptive gate bias circuit improves the evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) about 7 dB at a mid power region and 2.5 dB at a high power over a constant bias for the same LTE signal.

Fully Integrated CMOS Saturated Power Amplifier With Simple Digital Predistortion

A highly efficient CMOS saturated power amplifier (PA) is implemented. The efficiency is enhanced by the voltage waveform engineering using the second harmonic component generated by the nonlinear output capacitor (Cout). For an improved linearity to satisfy the specification of handset applications, a simple open-loop digital predisortion algorithm is employed. The fully integrated single-stage differential PA including the output transformer is fabricated using a 0.18- μm CMOS process. The PA with 3.5 V supply delivers good performance across the 1.7-2.0 GHz frequency band.

Investigation of Intermodulation Distortion of Envelope Tracking Power Amplifier for Linearity Improvement

An intermodulation distortion of an envelope tracking (ET) power amplifier (PA) is investigated in this paper. For this purpose, the distortion characteristics are simulated based on the inter-connection model between the PA and supply modulator. For the sweet spot tracking ET operation, the fifth-order distortion is the most important one, which is generated by AM-PM nonlinearity. To reduce the distortion, the phase compensation network (PCN) is proposed. The efficiency of the PA is also improved by a properly designed bias circuit. For demonstration purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and a 0.18- μm CMOS process, respectively. The ET PA is tested at 1.85 GHz using a long-term-evolution signal with 10-MHz bandwidth, a 7.5-dB peak-to-average power ratio, and 16 quadrature amplitude modulation. The ET PA with the proposed PCN and the bias circuit delivers a power-added efficiency of 44.3%, a gain of 23.4 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of -38.4 dBc, and an error vector magnitude of 1.8% at an average output power of 27 dBm. The multiband characteristics of the proposed ET PA are measured across 1.7-2.0 GHz. These results are achieved without any digitally supported techniques, indicating that the design approach is a promising technique for handset ET PA applications.

Wide-band CMOS loop-through amplifier for Cable TV tuner

A fully integrated loop-through amplifier (LTA) for cable TV tuner is presented in a 0.18 mum CMOS process. It covers the whole frequency band from 48 MHz to 860 MHz and allows a second TV and multiple tuners. This circuit employs a parallel connection of common-gate and common-source (CG-CS) amplifiers for broadband matching. The performances are enhanced by current amplification for high linearity and by noise canceling for low noise figure. There are global and local feedback circuits to achieve wide-band input matching and flat gain. We have achieved a gain of 5 dB, a noise figure (NF) of 8.2 dB, an IIP2 of 78 dBmV, an IIP3 of 59 dBmV and SR11 of -11 dB at 850MHz. The power consumption of the circuit is 92.4mW from a 3.3-V supply and the area of chip is 0.075mm2.