Lane Brooks

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.

A Zero-Crossing-Based 8b 200MS/s Pipelined ADC

A zero-crossing-based 8b 200MS/S pipelined ADC is implemented in a 0.18 mum CMOS process. It uses dynamic zero-crossing detectors and digital FFs that replace the functions of opamps and comparators. The ADC draws no static current. The power consumption is 8.5mW. The FOM is 0.51pJ/step

Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation

A method of indirect background digital calibration of the dominant static nonlinearities in pipelined analog-to-digital converters (ADC) is presented. The method, called decision boundary gap estimation (DBGE), monitors the output of the ADC to estimate the size of code gaps that result at the decision boundaries of each stage. Code gaps result from such effects as capacitor mismatch, finite opamp gain, finite current source output impedance, comparator offset, and charge injection. DBGE does not require special calibration signals or additional analog hardware and can even reduce the performance requirements of the analog circuitry. The calibration is performed using the input signal and thus requires that the input signal exercise the codes in the vicinity of the decision boundaries of each stage. If it does not exercise these codes, then lack of calibration is less critical because the nonlinearities will not appear in the output signal. DBGE is simple and amenable to hardware and/or software implementations. Simulation results indicate DBGE is highly accurate, robust, and adaptive even in the presence of parameter drift and circuit noise.

A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration

This paper describes a 12-bit zero-crossing based pipeline 100-MS/s ADC. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 0.32 mm2. The capacitor mismatch is calibrated by decision boundary gap estimate algorithm that runs in the background. It achieves an ENOB of 10.2 bits for a 49 MHz input signal and dissipates 6.2 mW from a 1.2V supply for a FOM of 53fJ/step.

A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS

A fully-differential zero-crossing-based 10b 26 MS/s pipelined ADC in a 65 nm CMOS process is presented. Switched-capacitor overshoot correction is compatible with the differential topology and allows faster operation. A CMFB is engaged in the coarse phase for constant common-mode. The 0.33 mm2 ADC achieves 54.3 dB SNDR with a FOM of 161 fJ/step.

Zero-Crossing-Based Ultra-Low-Power A/D Converters

Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal-oxide-semiconductor A/D converters from a fundamental thermal noise standpoint.