Hailang Liang

Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model

Abstract Gate underlap structure can be utilized to improve the immunity to short channel effects in MOSFET devices. In this work, gate underlap design scheme in cylindrical gate-all-around MOSFETs is explored based on an analytical model. This model takes into account the fringing field from gate electrode to underlap regions based on conformal mapping and a channel length transformation method. By solving Poisson equations in the underlap and channel regions and matching the boundary conditions, this model reproduces the channel potential profile in subthreshold operation region. Both symmetric and asymmetric underlap structures are covered. The developed model is verified extensively with TCAD simulations. A gate underlap design scheme is then provided based on this analytical model.

Distortion analysis of ultra wide-band diode bridge track and hold amplifier

Volterra analysis of the wide-band diode bridge track and hold amplifier (THA) is proposed based on a high frequency Schottky diode model. Approximate expressions for the third-order harmonic distortion and the third-order intermodulation distortion are derived respectively. Simulations based on a commercial available 130 nm process technology are performed with the SpectreRF circuit simulator. Comparative SpectreRF simulated results for the diode bridge THA have shown good agreement with those of Volterra series analysis.

Multi-frequency Test for analog circuits

In this paper, multi-frequency test is presented, which can maximize differences between the failure state and the normal state of the analog circuits response. Using sensitivity analysis, the multi-frequency test vectors of the circuit under test(CUT) are generated and chosen. The experimental results show that this approach is very effective and highly practical for multi-frequency test vectors of the analog circuits.

Noise analysis in ultra high speed CMOS track and hold circuit

Noise performance of the switched source follower (SSF) track and hold (T/H) circuit is analyzed. Approximate expressions for the output noise of the track mode and hold mode of the T/H circuit are derived respectively. Simulations based on a commercial available 65 nm process technology are implemented with the SpectreRF circuit simulator. It is shown that the noise contribution from the parasitic capacitance is significant at ultra high frequency and the dominant noise of the SSF T/H circuit is the KT/C thermal noise. Simulations also indicate that noise contribution in track mode is more than that in hold mode and locate the major noise contributor in the SSF T/H circuit.

A MATLAB program for Volterra distortion analysis in CMOS switched source follower

A MATLAB program for Volterra distortion analysis of ultra high speed weakly nonlinear circuit is presented. A Volterra series method and a nodal formulation are used in this program. Approximate expressions for the transfer function, the harmonic equations and third-order intermodulation distortion equation are given respectively. Simulations based on a commercially available 65 nm CMOS process technology are performed with both the Matlab program and the SpectreRF circuit simulator. It is shown that results obtained by the MATLAB program have a consistent match with those derived from SpectreRF simulator, whereas the overall computational efficiency has been improved.

Distortion analysis and calculation of wide-band track and hold amplifier

A Python computer program for calculation of distortion in the wide-band diode bridge track and hold amplifier (THA) is proposed. The computer program calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method with an improved process. Simulations based on a commercially available 130 nm process technology are performed with the SpectreRF simulator. Comparative SpectreRF simulated results for the diode bridge THA have shown good agreement with those of computer program calculation, whereas the overall computational efficiency has been improved in a special evaluation.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

A nano-metallic-particles-based CMOS image sensor for DNA detection

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano-metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 μm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.