Yun Ye

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process. By understanding the physical principles of atomistic simulations, we: 1) identify the appropriate method to divide a nonuniform gate into slices in order to map those fluctuations into the device model; 2) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth ; 3) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations; and 4) investigate the interaction with non-rectangular gate (NRG) and reverse narrow width effect (RNWE). The proposed SPICE simulation method is validated with atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.

Simulation of random telegraph noise with 2-stage equivalent circuit

With the continuous reduction of CMOS device dimension, the importance of Random Telegraph Noise (RTN) keeps growing. To determine its impact on circuit performance and optimize the design, it is essential to physically model RTN effect and embed it into the standard simulation environment. In this paper, a new simulation method of time domain RTN effect is proposed to benchmark important digital circuits: (1) A two-stage L-shaped circuit is proposed to generate RTN signal by integrating a white noise source. An L-shaped circuit is a RC filter connected with an ideal comparator, where RC values are calibrated with the physical property of RTN; (2) This sub-circuit is fully compatible with SPICE, enabling the time domain analysis in nanometer scale digital design; (3) The importance of discrete RTN is demonstrated on a 32nm SRAM design and a 22nm low power ring oscillator (RO), using the proposed method. As compared to traditional 1/f noise, the impact of RTN is more significant under low voltages, leading to tremendous differences in the prediction of Vccmin and failure probability in SRAM, as well as jitter noise in RO.

Variability analysis under layout pattern-dependent rapid-thermal annealing process

Rapid-Thermal Annealing (RTA) with radiation heating is recently adopted in nanoscale CMOS fabrication in order to achieve ultra-shallow junction with maximum dopant activation rate. However, recent results report the systematic shift of threshold voltage (Vth) and increased Vth variation due to RTA process. The exact amount of variations depends on layout pattern density, RTA heating temperature (T) and effective annealing time. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. With the new simulation capability, we recognize two major variation mechanisms under RTA: the change of effective channel length (Leff) induced by lateral dopant diffusion, and the fluctuation of equivalent oxide thickness (EOT) due to incomplete dopant activation. We perform device simulations to quantify transistor performance shift due to Leff and EOT variations. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization. The new tools are validated with published silicon data at 45 nm and 65 nm nodes. They will facilitate physical designers to predict and mitigate circuit performance variability due to the layout-dependent RTA process.

Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model

Abstract Gate underlap structure can be utilized to improve the immunity to short channel effects in MOSFET devices. In this work, gate underlap design scheme in cylindrical gate-all-around MOSFETs is explored based on an analytical model. This model takes into account the fringing field from gate electrode to underlap regions based on conformal mapping and a channel length transformation method. By solving Poisson equations in the underlap and channel regions and matching the boundary conditions, this model reproduces the channel potential profile in subthreshold operation region. Both symmetric and asymmetric underlap structures are covered. The developed model is verified extensively with TCAD simulations. A gate underlap design scheme is then provided based on this analytical model.

Compact modeling of Fe-FET and implications on variation-insensitive design

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers [1–2]. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure [3–5]. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper: (1) A new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET; (2) It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kanes expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

Intrinsic Variability and Reliability in Nano-CMOS

Introduction It is widely recognized that process variations and reliability issues will have profound impact on nearly all aspects of future IC design. Depending on their sources, they are often categorized into two types: intrinsic fluctuations and process-induced change [1][2]. Processinduced variations are caused by the imperfection in silicon fabrication, varying from foundries to foundries. On the other side, intrinsic variability and reliability, induced by atom-level charge and geometry fluctuations, are inherent to the device structure. They are limited by fundamental physics, posing one of the ultimate barriers to continual technology scaling. Examples of intrinsic variations include random dopant fluctuation (RDF), line edge roughness (LER), oxide thickness fluctuation (OTF), and bias temperature instability (BTI) [1]-[3]. Their importance is rapidly increasing as device feature size approaches the atom dimension.

Research progress on core-shell nanowire FETs

Silicon-based nanowire CMOS with the core-shell structure has not only excellent short-channel effect and enhanced conductance capability due to reduced scattering effect and unique low-dimensional structure, but also is compatible with the traditional CMOS processing, thus, it may be the promise one among the bulk MOSFET alternatives to extend CMOS integrated circuit into 10nm generation beyond. The work in the ULTRA group explored the novel structure, transport mechanism, simulation tool and compact modeling, strain effect, energy band engineering, so to develop the core-shell nanowire device physics theory, provide the new simulation tool, build an efficient compact model, and establish new fine process integration technique. The work deliverables will help device scientists and circuit designers deeply understand the potential and function of the silicon-based core-shell nanowire FET application beyond 10nm CMOS integrated circuit, know how to realize the optimized circuit performance from the fine processing technology and design.

The potential of Fe-FET for robust design under variations: A compact modeling study

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper, a new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET. It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.