Caixia Du

A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

A high-voltage lateral double-diffused MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. In the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce two additional electric field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a higher electric field is induced into the BOX layer, which can achieve a higher vertical BV. As a consequence, the BV is enhanced significantly. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and thus, the ON-resistance (RON) is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and RON is reduced by 10.2% and 14.7% in comparison with the conventional PSOI and buried n-type layer PSOI, respectively.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kanes expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

A new 600V partial SOI LDMOS with step-doped drift region

A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with SDD in partial PSOI (SDD-PSOI) is analyzed by 2-D numerical simulations, compared with conventional SOI (CSOI) and conventional PSOI (CPSOI) LDMOS transistors. The results indicate that the proposed structure can significantly improve BV up to 607V and reduce on-resistance by 12.6% in comparison to CPSOI.

Nonlinear parameterized model order reduction method for synthesis and optimization of VLSI circuits

A parameterized model order reduction technique for nonlinear VLSI circuit system is presented in this paper, which combines the Proper Orthogonal Decomposition (POD) with the interpolation method and hence overcomes the inefficiency of POD in representing parameterized nonlinear functions. In order to capture the accuracy of the parameterized reduced model over a large range of parameter values, a training scheme is proposed to automatically select the training parameter points by the greedy sampling method. Results show that the accuracy and efficacy are improved in the proposed nonlinear parameterized reduction method.

Study on silicon window polarity of partial-SOI LDMOS power devices

The Effect of silicon window polarity on partial-SOI (partial silicon-on-insulator, PSOI) LDMOS power devices under high-voltage operation is studied. Different polarities of the silicon window in PSOI LDMOSFETs are analyzed to investigate their effects on electrical characteristics: breakdown voltage (BV) and on-resistance (Ron). In partial-SOI LDMOSFETs, the P-type silicon window is considered as a part of the substrate, while the N-type silicon window falls into the drift region, which affects the high-voltage operation of devices. The two-dimensional (2-D) simulation results show that the breakdown voltage of PSOI LDMOSFET with P-type window is higher than that of PSOI LDMOSFET with N-type window, while the on-resistance of PSOI LDMOSFET with P-type window is lower than that of PSOI LDMOSFET with N-type window.

The effects of elliptical gate cross section on carbon nanotube gate-all-around field effect transistor

In this paper, the gate-all-around carbon nanotube field effect transistor (FET) with elliptical shaped gate is studied with numerical simulation to explore the gate dielectric variation effects. The simulations are carried out with the three dimensional self-consistence Poisson-Schrodinger equations with the non-equilibrium Greens function method. The on current, potential distribution, local density of states, and transmission coefficients of the devices of different geometry are examined. The performances of elliptical shaped gate device are compared to the round shaped gate ones and it is observed that the geometry has notable effects on the characteristics of the devices.

Distortion analysis and calculation of wide-band track and hold amplifier

A Python computer program for calculation of distortion in the wide-band diode bridge track and hold amplifier (THA) is proposed. The computer program calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method with an improved process. Simulations based on a commercially available 130 nm process technology are performed with the SpectreRF simulator. Comparative SpectreRF simulated results for the diode bridge THA have shown good agreement with those of computer program calculation, whereas the overall computational efficiency has been improved in a special evaluation.