Hong-Sun Hwang

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termination) is also presented.

A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.

A 1.0 V 256 Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes

A 1.0 V, 256 Mb SDRAM is designed in a 0.1 /spl mu/m CMOS technology. For low voltage applications, an offset compensated direct current sensing scheme improves refresh time as well as sensing performance. A charge-recycled precharge reuses the word-line discharge current to generate the boosted voltage required for equalization without charge pumping. At 1.0 V, the access time is 25 ns and the current is 15 mA.

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps /spl times/ 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write without 10 pre-charge scheme was employed. The power consumption and area of the chip are 2.4W and 7.2/spl times/10.2mm/sup 2/ respectively.