Uk-Rae Cho

A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-/spl mu/m 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

This paper presents a heterogeneous configuration of two different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of quad-core CPUs are implemented in one mobile application processor. The first type quad-core CPU is designed to give the highest performance at the cost of reasonable power consumption. The second type quad-core CPU is optimized with emphasis on energy efficiency than high performance. This paper addresses the design features for high-performance quad-core CPU and the design optimization issue for low-power quad-core CPU. The best performance shows 1.8X of performance at the lowest power. The lowest power is reduced to 1/5 of power at the highest performance. Our heterogeneous configuration of separate implementations can be a more efficient solution for different power and performance requirements of various mobile applications.

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

The proliferation of high-performance mobile devices is growing exponentially around the world. The essential driving force behind these ubiquitous devices is the high-performance CPU. To satisfy ever growing consumer demand for higher performance, a high-speed and multicore CPU configuration is mandatory, while energy efficiency is equally important for longer battery life. Furthermore, in order to support the wide range of performance (compute-intensive tasks, as well as less intensive tasks) required by todays mobile devices, a heterogeneous dual-CPU configuration comprising a high-performance CPU and an energy-efficient CPU can be one of the most energy efficient solutions for accomplishing both high-intensity and low-intensity tasks.

A 32nm high-k metal gate application processor with GHz multi-core CPU

Samsungs next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs are needed to meet this demand. Furthermore, mobile GPU performance is becoming increasingly important as mobile game graphics requirements are pushing the limits of GPU capabilities. For an enhanced mobile game user experience, a multi-core GPU is required. CPU/GPU power efficiency for longer battery life has been a major interest to consumers for many years. In order to support higher performance and power efficiency, two 64b quad-core CPUs with different microarchitectures and a hexa-core GPU are implemented using Samsungs 20nm gate-last high-k/metal-gate (HKMG) process.

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface

A new programmable and automatically adjustable off-chip driver (OCD) and on-die terminator (ODT) for DDR3-SRAM interface are proposed, to widen the valid data widow. The proposed OCD fills the role of the ODT, and the OCD and the ODT play a role in the ESD protection circuit. This application of 72 Mb DDR3-SRAM provides a 1.5 GHz data rate, and the valid data window of the DDR input signal is 540 ps. The proposed programmable impedance controller (PIC) maintains constant resistance of the ODT within a 3% variation, and supports DDR3-SRAM mode. A new scheme of updating impedance control codes to maintain uniform impedance and a stable power-up sequence for the ODT are also suggested.

Modeling and testing of faults in TCAMs

This paper proposes novel fault models for ternary content addressable memories (TCAMs) regarding both physical defects and functional fault models. Novel test algorithms which guarantee high fault coverage and small test length for detecting the faults in high density TCAM cell array is also proposed. The proposed TS−−T algorithm is suitable for detecting physical faults with compact test patterns and provides 92% fault coverage with small test length. Also, the proposed TM−−T algorithm makes it possible to detect various bridging faults among adjacent cells of high density CAMs. The test access time is (10 * l * 3 + 3 ) * write time and (12 * l * 3) * compare time in a n word by l bit TCAM.

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

This paper presents a digitally controlled oscillator (DCO) for high speed ADPLLs. The proposed DCO circuit has control codes of thermometer type, which can reduce jitters. Performance of the DCO is verified through a novel ADPLL. The ADPLL chip with the DCO was fabricated using a 0.18mum CMOS technology. The ADPLL has operation range between 520MHz and 1.5GHz and has 76ps peak-to-peak jitter at 668MHz

A SRAM Core Architecture with Adaptive Cell Bias Scheme

This paper describes an adaptive cell bias scheme that is proposed to achieve high performance and stability for a low power, high speed, and high density SRAM core with less process variation. The proposed scheme is featured with constrained-successive cell bias optimization method that determines the optimal cell bias condition sequentially to meet both the speed and stability target of a given SRAM core. The architecture with adaptive cell bias scheme is applied to a 144Mb double stacked S3 SRAM and leads to 49% reduction in SRAM core performance parameter variations with 8% area overhead. The power reduction is 21%

A Low Jitter ADPLL for Mobile Applications

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 μm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.