Hamed Abbasizadeh

Digital Error Correction for a 10-Bit Straightforward SAR ADC

This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS 0.18-μm technology. This structure consumed 140μW and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step.

A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator

A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparators delay variations is presented. The designed circuit uses a new bandgap reference to generate the reference voltage required by relaxation oscillator which allow variations due to voltage and temperature to be compensated. Another merit of this oscillator is that the phase noise at low-offset frequency is suppressed by the voltage integral feedback circuit. The frequency of the relaxation oscillator is determined by the RC response time. Thus, the current and capacitance are controlled by temperature and process compensation circuits to compensate for the frequency variation. The ROSC is implemented in a 0.18μm CMOS technology and its active area is 0.14mm2. The target frequency is 25MHz and current consumption is 22μA, where VDD is 1.8V. The oscillation frequency variation for VDD ranges from 1.4 to 1.9V is 0.2% and for temperature ranges from -40 to 125°C is 0.18%.

A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V reg for the BG core and Op-Amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.

A Single Inductor Dual Output Synchronous High Speed DC-DC Boost Converter using Type-III Compensation for Low Power Applications

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within 58μs.The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW&, 230mW respectively.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

A 10-bit 10MS/s differential straightforward SAR ADC

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with 0.18μm complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver

This paper presents a 12-bit 750KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for wireless portable device. The scheme of the ADC is based on a Dual-Sampling Capacitive DAC technique, low power dynamic latch comparator with Adaptive Power Control (APC) and bootstrap switch to reduce chip area and power consumption. The proposed 12-bit dual sampling CDAC topology reduces switching energy-efficient compared with 12-bit conventional SAR ADC. The prototype SAR ADC was implemented in Dongbu HiTek 0.18μm CMOS technology and occupies 0.68 mm2. The post-layout simulation results show the proposed ADC achieves an ENOB of 11.196 bit at a sampling frequency 750KS/s. It consumes only 0.48mW from a 5.0V supply and achieves the INL and DNL +1.45/-0.65 LSB and +1.0/-1.0 LSB respectively, SNDR 69.16dB, SFDR 78.18dB, and figure of merit (FoM) of 273 fJ/conversion-step.