Keum Cheol Hwang

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc-dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc-dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm × 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc-dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3-20 V, and the efficiency of the WPRU is about 80.86%.

Circularly Polarized Spidron Fractal Dielectric Resonator Antenna

In this letter, a circularly polarized Spidron fractal dielectric resonator antenna is presented. A wide 3-dB axial ratio (AR) bandwidth is realized by merging a Spidron fractal dielectric resonator and a C-shaped slot that can produce circular polarization. The proposed antenna is excited through the coupling between a C-shaped slot in the ground plane and a 50-Ω microstrip feeding line. A prototype of the antenna is fabricated and tested. Reasonable agreement is achieved between the measurement and simulation. The experimental results show that the proposed antenna has a -10- dB reflection bandwidth of 37.29% (4.32-6.30 GHz) and a 3-dB AR bandwidth of 11.57% (5.13-5.76 GHz). The measured gain of the antenna ranges 2.20 dBic to 3.16 dBic within the AR bandwidth.

Circularly Polarized Semi-Eccentric Annular Dielectric Resonator Antenna for X-Band Applications

In this letter, a compact single-feed circularly polarized dielectric resonator antenna is proposed for X-band applications. The radiator comprises a semi-eccentric annular dielectric resonator (DR), which is a semi-elliptical DR with a hollow elliptical cylinder. A vertical coaxial probe is located adjacent to a cutting surface of the DR to excite the proposed antenna. The two main design parameters, the aspect ratio of the elliptical DR and the feeding position, were optimized, and a prototype of the antenna was fabricated and tested. The experimental results exhibit a -10-dB reflection bandwidth of 29.14% (9.41-12.62 GHz) and a 3-dB axial-ratio bandwidth of 5.71% (10.37-10.98 GHz). The measured peak gain varies from 4.17 to 4.78 dBic.

Broadband Doherty Power Amplifier Based on Asymmetric Load Matching Networks

This brief presents asymmetric load matching networks for broadband Doherty power amplifiers (DPAs). The output combiner consists of two λ/4 impedance transformers with optimized characteristic impedance values in order to provide a load modulation at a high output power level; the bandwidth limitation for efficiency at the back-off power level can be then mitigated. For a proper load modulation with the proposed output combiner, asymmetric load matching networks between the carrier and peaking amplifiers are proposed. The input and output matching networks were designed using balanced open stubs, which are more insensitive to frequency than unbalanced open stubs. For the load matching networks, two-section matching networks were adopted. The designed and implemented broadband DPA showed a fractional bandwidth of 23.5% (from 750 to 950 MHz). It also showed measured efficiency values of higher than 55.4% at the peak power level and 51.5% at the 6-dB back-off power level, respectively. For the operational frequency range, a peak output power value of higher than 48 dBm and a gain of 14-15.8 dB were achieved.

Self-Energy Recycling for RF Powered Multi-Antenna Relay Channels

We investigate self-energy recycling (S-ER)-based RF powered multi-antenna relay channels (RCs) for the coverage extension in sensor networks or small cells. In the S-ER-based RF powered RC, the power used at the relay station for data transmission depends only on the energy from the access point and the recycled energy from its own transmission. We propose an optimal beamforming scheme with associated protocols and study their behaviors for both cases of downlink only and joint up–down link. Strategies for the power allocation between data transmission and RF powering are provided and a comparison with the conventional RF powered RC is made. For the proposed power allocation strategies, the performance of the conventional RC is achieved by the proposed RF powered RC only when infinite RF power is available. A high value of S-ER helps the proposed systems to reach the performance of conventional relay systems. In the joint up–down link protocol, we show that the up–down rate region can simply be constructed with easy power allocation strategy.

A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS

This brief presents a wide-locking-range injection-locked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dual-injection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the ILFD is automatically digitally calibrated to reflect the frequency of the injected signal from the voltage-controlled oscillator. To control the frequency of the ILFD, the load current is digitally tuned with 3-bit control signal. The ILFD is fabricated using 65-nm CMOS process, and by tuning the load current, it achieves the wide operation frequency range of 14.1-45.8 GHz. When the input signal of 30 GHz is injected, the locking range of the ILFD is 7.2 GHz, while the power consumption is 2.5 mW from a 1-V supply voltage.

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18-μm CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.

Doherty Power Amplifier Based on the Fundamental Current Ratio for Asymmetric cells

This paper presents a Doherty power amplifier (DPA) based on asymmetric cells using an even input power drive and an appropriate peak fundamental current ratio (FCR) between the peaking amplifier and the carrier amplifier. Using an appropriate output combiner and an even input power drive for the DPA, not only better load modulation but also enhanced power gain can be achieved. After providing an analysis for the fundamental currents, a design guide for the proposed DPA using the peak FCR is presented. For verification, conventional and proposed DPAs were designed using GaN-HEMTs for the 2.14-GHz band. Using a downlink long-term evolution signal having a peak-to-average power ratio of 6.5 dB, comparably better performances were achieved than the conventional DPAs, such as a high power-added efficiency of 55.7% and a power gain of as high as 16.6 dB, at an average output power level of 36.9 dBm.

A Wideband Circularly Polarized Pixelated Dielectric Resonator Antenna

The design of a wideband circularly polarized pixelated dielectric resonator antenna using a real-coded genetic algorithm (GA) is presented for far-field wireless power transfer applications. The antenna consists of a dielectric resonator (DR) which is discretized into 8 × 8 grid DR bars. The real-coded GA is utilized to estimate the optimal heights of the 64 DR bars to realize circular polarization. The proposed antenna is excited by a narrow rectangular slot etched on the ground plane. A prototype of the proposed antenna is fabricated and tested. The measured −10 dB reflection and 3 dB axial ratio bandwidths are 32.32% (2.62–3.63 GHz) and 14.63% (2.85–3.30 GHz), respectively. A measured peak gain of 6.13 dBic is achieved at 3.2 GHz.

A Triple-Mode Wireless Power-Receiving Unit With 85.5% System Efficiency for A4WP, WPC, and PMA Applications

This paper presents the design of a triple-mode wireless power-receiving unit (TWPRU) for battery charger with high efficiency. The TWPRU is proposed based on Alliance for Wireless Power (A4WP), Wireless Power Consortium (WPC), and Power Matters Alliance (PMA) standards. An adaptive alignment gate controller technique is proposed in the triple-mode active rectifier to block the reverse leakage current and improve the power conversion efficiency (PCE). This technique can compensate for the delays in the gate control signals of the main switching mosfets at different operating frequencies for A4WP, WPC, and PMA. The dead time of a dc–dc converter is optimally determined depending on the voltage and the temperature variations by phase calibration circuit. This chip with an active area of 5.0 mm × 3.5 mm is implemented in 0.18-μm BCD technology. The maximum PCEs of the triple-mode active rectifier are 91.7% in the A4WP mode and 92.7% in the WPC/PMA mode, respectively. The maximum PCE of the dc–dc converter is 92.3% at a load current of 500 mA, while the system efficiencies of TWPRU at A4WP and WPC/PMA modes are about 84.5% and 85.5%, respectively.