Hang Guan

CMOS-compatible highly efficient polarization splitter and rotator based on a double-etched directional coupler

We present a highly efficient polarization splitter and rotator (PSR), fabricated using 248 nm deep ultraviolet lithography on a silicon-on-insulator substrate. The PSR is based on a double-etched directional coupler with a length of 27 µm. The fabricated PSR yields a TM-to-TE conversion loss better than 0.5 dB and TE insertion loss better than 0.3 dB, with an ultra-low crosstalk (-20 dB) in the wavelength regime 1540-1570 nm.

Ultracompact silicon-on-insulator polarization rotator for polarization-diversified circuits.

We present an ultracompact (15.3 μm long) and high-efficiency silicon-on-insulator polarization rotator designed for polarization-diversified circuits. The rotator is comprised of a bilevel-tapered TM0-to-TE1 mode converter and a novel bent-tapered TE1-to-TE0 mode converter. The rotator has a simulated polarization conversion loss lower than 0.2 dB and a polarization-extinction ratio larger than 25 dB over a wavelength range of 80 nm around 1550 nm. The rotator has a SiO2 top-cladding and can be fabricated in a CMOS-compatible process.

High-Efficiency Grating Couplers Near 1310 nm Fabricated by 248-nm DUV Lithography

We demonstrate a highly efficient grating coupler with center wavelength near 1310 nm fabricated on a silicon-on-insulator (SoI) wafer by 248-nm deep ultraviolet lithography. One of the lowest reported losses of 2 dB is achieved using feature sizes of 200 nm and without other process enhancements, such as polysilicon. The higher efficiency is obtained through improved mode-matching based on a novel genetic algorithm, which utilizes two different etch depths. The 3-dB bandwidth is 50 nm, and the back-reflection to the waveguide is better than 20 dB. The result shows low-loss coupling between waveguides and single-mode fibers for 1310~nm applications suitable for mass production on the commonly used 220-nm SoI platform.

High-Efficiency Biwavelength Polarization Splitter-Rotator on the SOI Platform

We present the design of a highly efficient polarization splitter-rotator that operates at both 1310- and 1550-nm wavelength bands in a 220-nm silicon-on-insulator platform. The proposed polarization splitter-rotator has a simulated insertion loss of -0.9 dB at 1310 nm and -1 dB at 1550 nm. This is the first theoretical demonstration of a biwavelength polarization splitter-rotator. This letter is valuable for the implementation of a novel edge-coupling-based light duplexing silicon photonic system.

A software-defined optical gateway for converged inter/intra data center networks

We present a software-defined optical gateway for converged inter/intra data center networks. The optical gateway enables transparent rack-to-rack connectivity across data centers through WDM channels. Sub-second reconfiguration time and wavelength defragmentation are experimentally demonstrated.

Silicon photonic memory interconnect for many-core architectures

A scalable and flexible memory interconnect is a key component for a many-core architecture to take full advantage of the high-bandwidth of multiple memory stacks. In this paper, we discuss both technological and architectural challenges of these processor-to-memory interconnects, and focus on two important issues of many-core memory accesses: traffic hotspots and non-uniform memory access (NUMA). We propose a reconfigurable Silicon photonic memory interconnect based on 2.5D stacking that can direct memory traffic to any memory interface on the processor, thus alleviating the two aforementioned effects in addition to providing high bandwidth. Simulations based on a 16-core 4-memory model show that the proposed architecture can lead to up to 2× STREAM speedup over fixed connections in both hotspot and NUMA scenarios. We also demonstrate the proposed architecture using a four-port Silicon photonic demultiplexer and a 4×4 synthesizable on-chip fabric called OpenSoC. The FPGA-emulated system demonstrates dynamic memory rewiring through wavelength routing, and achieves a reconfiguration time of 5 microseconds.

Symmetrical polarization splitter/rotator design and application in a polarization insensitive WDM receiver

In integrated photonics, the design goal of a polarization splitter/rotator (PSR) has been separating the TE0 and TM0 modes in a waveguide. This is a natural choice. But in theory, a PSR only needs to project the incoming State Of Polarization (SOP) orthogonally to its output ports, using any orthogonal mode basis set in the fiber. In this article, we introduce a novel PSR design that alternatively takes the linear combination of TE0 and TM0 (TE0 +/- TM0) as orthogonal bases. By contrast, existing approaches exclusively use TE0 and TM0 as their basis set. The design is based on two symmetric and robust structures: a bi-layer taper and a Y-junction, and involves no bends. To prove the concept, we incorporated it into a four-channel polarization insensitive wavelength division multiplexing (PI-WDM) receiver fabricated in a standard CMOS Si photonics process. 40 Gb/s data rate and 0.7 +/- 0.2 dB polarization dependent loss (PDL) is demonstrated on each channel. Lastly, we propose an improved PSR design with 12 μm device length, < 0.1 dB PDL, < 0.4 dB insertion loss and < 0.05 dB wavelength dependence across C-band for both polarizations. Overall, our PSR design concept is simple, easy to realize and presents a new perspective for future PSR designs.

Compact and low loss 90° optical hybrid on a silicon-on-insulator platform

We present a compact and low loss 90° optical hybrid on a silicon-on-insulator (SOI) platform for coherent receiving systems. Our 90° optical hybrid uses a novel topology, comprising one Y-junction and three 2x2 multimode interference (MMI) couplers. The geometry of the 90° optical hybrid is fully optimized using particle swarm optimization (PSO). The fabricated 90° optical hybrid has a compact footprint of 21.6 μm x 27.9 μm, with an insertion loss less than 0.5 dB, a common mode rejection ratio (CMRR) larger than 30 dB, and phase error smaller than 3° in the C-band across 22 reticles on one wafer. The measured phase error (< 3°) in a packaged coherent receiver further confirms the excellent performance of the 90° optical hybrid.

Experimental demonstration of converged inter/intra data center network architecture

We present a novel converged inter/intra data center network architecture to enable on-demand rack-to-rack connectivity across data centers. The hardware architecture includes a bidirectional software-defined optical gateway that aggregates racks or pods on a conventional data center data plane and provides both east-west and north-south connectivity. The software architecture consist of two Software-Defined Networking (SDN) agents over the data center and transport network control planes that manages connection requests and finds the optimal routing and wavelength configuration from the available WDM channels. We present bulk data transfer and Virtual Machine (VM) migration on a testbed of three data centers.

Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture

In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we first present a concept of optically connected memory modules, delivering enough bandwidth to allow for cache reduction and memory externalization. Second, we show that connecting these memory modules in a reconfigurable interconnect permit to substantially offload NoC traffic.