Hang M. Liaw

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.<<ETX>>

Purification of metallurgical-grade silicon by slagging and impurity redistribution

The purification of metallurgical-grade silicon (MGSi) was carried out by slagging and impurity redistribution through repeated melting and pulling. A Czochralski crystal puller was used for performing both functions. The slags consisting of CaOSiO2 and CaOMgOSiO2 were found to be effective for extracting aluminum from the MGSi melts. The repeated melting and pulling method was effective for the removal of other metallic impurities. When slagging and multiple pulling were combined, the thrice-pulled ingots contained an impurity concentration equivalent to that of semiconductor-grade silicon with the exception of boron and phosphorus.

An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n/sup -/ and p/sup +/ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n/sup +/ and p/sup +/ implants are annealed, resulting in MOSFETs with improved short-channel behavior due to the smaller lateral source/drain diffusion. >

3C-SiC buffer layers converted from Si at a low temperature

The authors have obtained single-crystal 3C-SiC films via conversion of the surface region of Si(111) and (100) wafers at 970 C by reaction with C{sub 2}H{sub 4} in an MBE reactor. The major defects in the films were clusters, voids, and misfit dislocations. Investigation by high resolution TEM images showed low lattice strains in the epitaxial layer due to the formation of 1 misfit dislocation for every 4 to 5 regular SiC planes that are bonded to Si at the interface. The clusters and voids often occurred in pairs. A model for forming the void-cluster pairs is suggested.

Effect of impurity gettering on the efficiency of metallurgical-grade silicon solar cells

The efficiency of thin film epitaxial solar cells deposited onto low cost metallurgical-grade silicon (MGSi) was improved by the impurity gettering of the MGSi substrates. The gettering techniques investigated include (i) work damage on the back side of the wafers, (ii) intrinsic gettering using a one- and two-step thermal anneal and (iii) phosphorus gettering. The effectiveness of the various gettering techniques is evaluated from the electrical characteristics of solar cells. A one-step thermal anneal improves the solar cell efficiency from 7.9% (air mass 1) to 11.2% for 50 μm epitaxial cells. A two-step anneal further improves the efficiency to 11.8%. The phosphorus gettering gives the same efficiency as a two-step anneal but with a shorter annealing time. The improvement in cell efficiency is attributed primarily to the increase in the fill factor and short-circuit current density Jsc. Work damage in addition to a two-step anneal did not improve the overall electrical characteristics. It was also found that the cell efficiency is improved on an increase in epitaxial layer thickness. MGSi and semiconductor-grade silicon (SGSi) substrates on which are deposited epitaxial layers of the same thickness give comparable electrical results. The annealing of SGSi considerably degrades the cell performance. Computer modeling is used to analyze the current-voltage curves for the components of current losses. The major current losses for the MGSi solar cells were due to bulk recombination.

Epitaxial Growth of AlN on Si Substrates with Intermediate 3C-SiC as Buffer Layers

Single crystalline AlN was successfully grown on a 3C-SiC coated Si (111) substrate by organometallic vapor phase epitaxy. The 3C-SiC film was obtained via the conversion of the Si near-surface region to SiC using gas-source molecular beam epitaxy. The quality of the AlN was mainly controlled by that of the SiC. The effects of Si pits and SiC hillocks formed during the conversion on subsequent AlN growth are discussed. Process optimization is suggested to improve the SiC buffer layer for subsequent AlN deposition.

Purification of metallurgical-grade silicon by the thermomigration of impurity clusters

Abstract A thermomigration technique was applied to purify metallurgical-grade silicon wafers which contain a high concentration ( e.g. more than 100 ppm) of metallic impurities. Wafers cut from the tang end of once-pulled ingots exhibiting a lamellar structure belong to this category. The method requires a high temperature gradient across the wafers with the temperature on the cooler side in excess of 1000 °C. At this temperature the clusters of impurities alloy with the silicon to form droplets. The droplets then migrate toward the hotter side of the wafers. Subsequent etching removes the alloyed impurities from the wafers. The effectiveness of this purification technique was directly analyzed by comparing emission spectroscopy data before and after thermomigration. An impurity reduction of at least one order of magnitude was achieved for such impurities as aluminum, iron, manganese, titanium and vanadium.