James R. Pfiester

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >

Electrical properties of heavily doped polycrystalline silicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P/sup +/) poly-Si/sub 1/spl minus/x/Ge/sub x/ is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si/sub 1/spl minus/x/Ge/sub x/. The resistivity of heavily doped n-type (N/sup +/) poly-S/sub 1/spl minus/x/Ge/sub x/ is similar to that of comparably doped poly-Si for x >

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.<<ETX>>

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p/sup +/ doped polysilicon gates. Boron penetration results in large positive shifts in V/sub FB/, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi/sub 2/ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO/sub 2/-Si interface. Elemental boron is shown to be superior to BF/sub 2/ as an implant species for surface channel submicron PMOS devices.<<ETX>>

PMOS transistors in LPCVD polycrystalline silicon-germanium films

P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature (<or=600 degrees C) process or a high-temperature (up to 950 degrees C) process. Poly-SiGe TFT technology allows the use of lower anneal temperatures and shorter anneal times as compared to a poly-Si TFT technology. The devices fabricated show good transistor characteristics after hydrogenation to reduce the number of electrically active traps in their active channel region.<<ETX>>

A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation.<<ETX>>

A variable-work-function polycrystalline-Si/sub 1-x/Ge/sub x/ gate material for submicrometer CMOS technologies

P/sup +/ poly-Si/sub 1-x/Ge/sub x/ is a promising candidate for the gate material in submicrometer CMOS technologies due to its improved resistivity and its work function (which can be modified to achieve more-scalable NMOS and PMOS devices). The work function of P/sup +/ poly-Si/sub 1-x/Ge/sub x/ decreases with increasing Ge content, by more than 0.3 V from 0 to 60%. Because of its ease of formation and compatibility with VLSI fabrication techniques, assimilating poly-Si/sub 1-x/Ge/sub x/ into an existing CMOS process should be relatively simple.<<ETX>>

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n/sup -/ junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed.<<ETX>>

A polycrystalline-Si/sub 1-x/Ge/sub x/-gate CMOS technology

A novel polycrystalline silicon-germanium gate CMOS process has been developed for a submicron CMOS technology. The incorporation of germanium into a heavily doped p-type polycrystalline-silicon (P/sup +/ poly-Si) gate material causes the gate work function to be reduced (more than 300 mV for a 60% Ge material), so that both NMOS and PMOS surface-channel devices may be achieved. In addition, it improves the gate sheet resistance by increasing dopant activation. Poly-Si/sub 1-x/Ge/sub x/ films with Ge mole fractions up to 0.6 were found to be completely compatible with standard VLSI fabrication processes in regard to deposition and patterning techniques, high-temperature chemical and mechanical stability, and electrical stability and uniformity.<<ETX>>