Craig D. Gunderson

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.<<ETX>>

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p/sup +/ doped polysilicon gates. Boron penetration results in large positive shifts in V/sub FB/, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi/sub 2/ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO/sub 2/-Si interface. Elemental boron is shown to be superior to BF/sub 2/ as an implant species for surface channel submicron PMOS devices.<<ETX>>

Characterization of polysilicon-encapsulated local oxidation

Device isolation has been most commonly achieved through the use of local oxidation of silicon (LOCOS) or LOCOS derivatives. LOCOS is a highly dependable, low-defect isolation technique, which explains its continued extensive use. Unfortunately, the inherently large oxide encroachment associated with LOCOS is not compatible with 0.8- mu m design rules. Many alternative isolation techniques designed to reduce oxide encroachment have been proposed. These alternatives often result in an increase in defectivity and/or process complexity. Polysilicon-encapsulated local oxidation (PELOX) utilizes a polysilicon-filled cavity self-aligned to the nitride edge to achieve oxide encroachment reduction. The physical (scanning electron and transmission electron micrographs) and electrical (electrical channel width, diode leakage, and gate oxide integrity) characterization of PELOX isolation are reported. >

A cobalt salicide CMOS process with TiN-strapped polysilicon gates

A submicrometer CMOS technology with MOSFET structures consisting of a TiN-strapped polysilicon gate electrode and self-aligned cobalt silicided source/drain junctions is developed. It is shown that the TiN-strapped gates provide a low-sheet-resistance gate electrode without threshold voltage instabilities caused by the lateral dopant interdiffusion of silicided gates. Cobalt silicide creep over the sidewall spacer, which can result in bridging between the source/drain and gate, is also eliminated. Since the source-drain regions are silicided with CoSi/sub 2/, shallow, low-leakage junctions are obtained.<<ETX>>

A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure.<<ETX>>

A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 /spl mu/m/sup 2/ with conventional I-line lithography and 7.32 /spl mu/m/sup 2/ with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 /spl mu/m active pitch, MOSFET transistors designed for a 0.80 /spl mu/m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. >

Disposable polysilicon LDD spacer technology

An advanced 0.5- mu m CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5- mu m CMOS technology features surface-channel LDD NMOS and PMOS devices, n/sup +//p/sup +/ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n/sup +/ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n/sup -/ and boron p/sup -/ regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3- mu m electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V. >

An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology

A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<<ETX>>

Gain-enhanced LDD NMOS device using cesium implantation

A gain-enhanced LDD NMOS device has been developed for a submicrometer CMOS technology. Using cesium implantation to create a fixed positive charge at the oxide/silicon interface above the LDD region, improvements in device gain are obtained without degradation to hot-carrier reliability or short-channel behavior. Since fixed charge rather than an extended polysilicon gate is used to overlap the LDD regions, no penalty is paid in terms of extra gate overlap capacitance. Furthermore, this structure is easily integrated into a conventional twin-tub CMOS process with the addition of only one cesium implantation step which is performed at the same time as the LDD n/sup -/ implant step. >

Optimization of two-dimensional collector doping profiles for submicron BiCMOS technologies

The authors demonstrate that the optimal 2-D collector doping profile for BiCMOS technologies is a strong function of the intended circuit application of the BJT (bipolar junction transistor). The 2-D collector doping profile in this study was tailored by selectively implanting the collector (SIC) into only the intrinsic region of the BJT. A controlled comparison between SIC and conventional collector implant devices was made by keeping BV/sub CEO/ and beta invariant. It is concluded that selectively implanting the collector into the intrinsic area is advantageous for low-current, but detrimental for high-current gates.<<ETX>>