Lingwei Zhang

An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications

An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A wireless capsule endoscopic system with a low-power controlling and processing ASIC

This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.

An energy efficient implementation of on-demand MAC protocol in medical Wireless Body Sensor Networks

This paper presents an energy-efficient implementation of a real-time on-demand MAC protocol for medical Wireless Body Sensor Network (WBSN). Medical WBSN is focused on pervasive healthcare and medical applications, such as monitoring vital signs, making basic drug delivery, etc. The sensor nodes in the heterogeneous WBSN generally require different data rates, due to their differing functions. Additionally, because of the strict resource constraints, the sensor nodes must be ultra-low-power. Thirdly, low-rate treatment-function nodes must also “work-on-demand” to prove proper activities in the slave nodes such as stimulus and drug delivery. These three requirements cannot currently be satisfied simultaneously in commonly-used single channel implementations because the channel monitoring consumes too much power for long-term use. In the proposed implementation, a secondary channel is introduced in, which is used for channel listening only. Benefiting from the secondary channel, the node can achieve both real-time “work-on-demand” and zero idle power, by means of recovering energy from the “demand token”. An elaborated energy-harvesting RF module achieves monitoring the secondary channel. The prototype system of sensor nodes is expected for the zero-idle-power and the response time of less than 2ms.

An energy-efficient ASIC with real-time work-on-demand for wireless body sensor network

This paper presents an energy efficient ASIC design with the capability of real-time work-on-demand, targeting on the applications of wireless body sensor network (WBSN), especially on those for medical and heath purposes. Application specific requirements have been reviewed. A novel type of sensor node architecture is proposed with a hybrid of active/passive transceivers. The passive RF receiver with zero standby current gives the WBSN nodes the real capability of work-on-demand which is not allowed in previous architectures. A power management module with an optimized power mode control scheme has also implemented to provide various supply voltages for the sensor nodes, and in addition this module can provide the sensor nodes a flexible power mode control for the purpose of energy saving. An ultra-low-power MCU which supports the proposed architecture has been integrated in the ASIC, which can perform the functions of media access, signal flow control and networking. The proposed architecture has been verified through FPGA experiments, and the ASIC has been designed and fabricated using a standard 0.18 um CMOS process. The designed ASIC occupies a die area of 2 mm times 2.5 mm. The digital core of this ASIC has 72.8 K equivalent gate counts excluding the memories. A typical WBSN sensor node can be built with this ASIC in together with a commercial RF transceiver, the sensor parts and some other components, and our ASIC can serve as the main control part for such a node.

A low-power DC offset calibration method independent of IF gain for zero-IF receiver

A novel low-power DC offset calibration (DCOC) method independent of intermediate frequency (IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency (RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.摘要本文基于新型直流失调模型提出了一种应用于零中频接收机的新型直流失调校准方法。 该方法相比于传统的方法, 可以使校准过程独立于零中频接收机的中频增益, 大大简化了校准的复杂度, 有效地降低了校准电路所占用的芯片面积, 节约了芯片成本。 该方法只需要进行一次校准, 平均功耗接近为零, 远低于传统方法的功耗。 基于该方法, 我们实现了一种直流失调校准电路, 实际测试结果与仿真吻合, 很好地证明了该方法的创新性和实用性。

A passive RF receiving and power switch ASIC for remote power control with zero stand-by power

A passive RF signal receiving and power switch ASIC is proposed, designed and verified for remote AC power switch. This IC receives 915 MHz RF signals containing power switching commands, and switches on/off the AC power relay of a household appliance accordingly. The proposed ASIC only uses energy recovered from the received RF signal, and it consumes almost zero stand-by current. The wireless identification technique is adopted to improve its anti-disturbance performance. The ASIC is designed in the 0.18 mum CMOS process, and it occupies a core area of 0.9 mm2. It can work with an RF input power as low as of 40 muW, and the data receiving rate is ~25 kbps. The measured standby current is less than 10 nA. The designed ASIC has been verified in a wireless switch demo system which can be used to switch a 220 V AC bulb remotely.

A lower power reconfigurable multi-band transceiver for short-range communication

A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented. Its low intermediate frequency (IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation. An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18 μm CMOS process. The measurement results at the maximum gain mode show that the receiver achieves a noise figure (NF) of 4.9/5.5 dB and an input 3rd order intermodulation point (IIP3) of −19.6/−18.2 dBm in 400/900 MHz band. The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50 Ω load. The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band, respectively.

A programmable low-pass filter with adaptive miller compensation for zero-IF transceiver

A programmable active-RC low-pass filter is presented with tunable bandwidth realized with a fast tuning circuit suited for a zero-IF transceiver. The filter adopts a 3rd-order Bessel low-pass architecture. Its -3dB bandwidth can be programmed to 250K, 500K, 1M and 2MHz.An operational amplifier with adaptive Miller compensation is designed to maintain the stability of the circuit when the filter is configured to work under different frequency bands. An on-chip automatic frequency tuning circuit is designed to compensate for the errors in on-chip resistance and capacitance caused by process, voltage and temperature variations. The circuit is designed in a 0.18-μm CMOS technology and the overall current consumption is 0.98mA with a supply voltage of 1.8V. The IIP3 is 26.5dBm and the fast automatic tuning requires only 40μs.