Hans Kristian Otnes Berge

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

High-Speed Serial AER on FPGA

The paper presents a high speed serial address-event representation (AER) link with a capacity of 41.66Mevents/sec. The link has been implemented using a low voltage differential signaling (LVDS) interface on a commercial FPGA. Many of the latest reconfigurable devices (FPGAs, CPLDs, etc.) offer highly optimized modules for this kind of communication. However, many AER processing systems require an ASIC implementation. The paper proposed to implement AER components with a serial AER interface as multi-chip PCBs with one or several ASICs communicating in parallel with an FPGA that handles the external high speed serial link. The authors judge the design effort to be much smaller than in a comparable monolithic ASIC implementation.

Benefits of decomposing wide CMOS transistors into minimum-size gates

In this paper we show how decomposition of a wide CMOS transistor into a multi-finger FET with gates of minimum size can be beneficial for the reduction of delay and power-delay products in logic gates. This design possibility, which we call a minimum-split transistor (MST), seems to be largely overlooked in the literature. In a 90 nm CMOS process we compare the design to wide transistors. By exploiting the narrow-width effect, reduced parasitic capacitances from a shorter active channel and increased gate-drain spacing, we achieve up to 75–85% higher operation speed at a similar or reduced power consumption. The worst-case timing delay is reduced by 35–40% along with the nominal values. The design technique is considered valuable, in particular for critical time paths. The paper takes the perspective of subthreshold logic design at 200 mV, but the technique is also useful above threshold. A statistical experiment also investigates how Vth variation in MSTs changes with the number of parallell gates.

Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach

In this paper we present design and optimization results of a 9T SRAM cell in a 65 nm low power technology, which previously has not been investigated for subthreshold operation. The cell is capable of both read and write operations on a supply voltage from 300mV to 1.2V. In our implementation the SRAM cell employs both high and low Vt devices for lower leakage and faster read operation. The current work focuses on operation of the cell as a single port SRAM, although extension to dual port is possible. To optimize and find trade-offs for SRAM performance in both voltage domains we use a multiobjective optimization method, where our design goals were robustness, leakage, operating speed and area. The optimization method provides an approximation of the set of all Pareto optimal designs. Based on this we may quickly select criteria for the objectives and easily optimize the rest of the parameters. Compared to recent publications the 9T cell of this paper shows promise of greatly reducing standby leakage power and good robustness while retaining a similar speed.

Muller C-elements based on minority-3 functions for ultra low voltage supplies

Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150mV, the simulated delays for the 12T and 24T implementations were 16.2 µs and 18.5 µs, respectively. The mean static power consumption figures were for the same conditions 2.6pW and 7.4pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150mV supply voltage. The switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300mV.

A Gate Leakage Feedback Element in an Adaptive Amplifier Application

This brief presents a method to exploit gate leakage (GL) to create a feedback element for an input offset insensitive and output offset programmable inverting amplifier. Measurements are shown from a test circuit produced in a 90-nm multithreshold CMOS process where a GL element uses thin oxide and a amplifier input stage uses thick oxide. The feedback element has very high nonlinear impedance from about 100 M to several gigaohms depending on the applied voltage, and is suitable for adaptive applications where long time constants (1 ms to 1s) are required and small, slowly wandering offsets can be tolerated.

Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation

Gate leakage that occurs in deep-submicrometer CMOS might be a convenient new way of implementing highly resistive elements with minimal area consumption. We present an adaptive device that exploits gate leakage in the 90-nm STM CMOS process for offset cancellation at its input. This is achieved by a high-pass-filtering input stage with a very low cutoff due to a time constant of approximately 130 ms. In this filter, three 0.1times0.22 mum2 gate-oxide structures are used to achieve the equivalent of a 6.5-GOmega resistance

Multi-objective optimization of minority-3 functions for ultra-low voltage supplies

Low supply voltages, small currents and small circuit feature sizes will for CMOS logic typically coincide with deteriorating robustness, i.e. a reduction of a circuits ability to maintain correct functionality across all operating conditions. In this paper we examine three circuit topologies implementing the minority-3 function, operating at a power supply voltage of 150 mV in a standard 65 nm CMOS process. Using a heuristic multiobjective optimization algorithm we consider each circuits area and metrics for power and robustness, and optimize each circuit to find an approximation to the optimal trade-off surface (a Pareto front) for these objectives.

Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

Development of an ASIC for the readout of CZT/CdTe radiation detectors in space

The IDE 4281 is an application specific integrated circuit (ASIC) that has been designed for the readout of CdTe/CZT radiation detectors in space. The chip can be used for single photon spectroscopy of x-rays and γ -rays with energy between 3.5 keV and 140 keV and rate up to 100 kcps per chip. The chip contains 12 low-noise pre-amplifiers (110 e equivalent noise charge, ENC), each followed by a pulse shaper (6 programmable peaking times from 0.75 μs to 4 μs) and a level comparator for triggering. The amplifiers are optimized for negative polarity input charge up to -5 fC. When a charge from the detector exceeds one of the adjustable thresholds, the chip delivers a data packet containing the address of the triggering channel and it delivers an analog signal proportional to the energy deposited by the photon in the detector. The chip requires positive and negative voltage supplies (+1.5 V and -2 V) and one reference bias current to generate its internal bias currents. The total power is 19 mW in idle state and 25 mW maximum. The chip has a 113-bit shift register, programmable via a serial interface, which allows one to set various functions, to program digital-to-analogue converters (DACs), and to tune parameters. Each channel has an optional compensation for detector leakage currents. All amplifier inputs are protected by diodes against over-voltage and electrostatic discharge (ESD). The engineering model (EM) and flight model (FM) ASICs have been designed and manufactured. The article describes the results obtained with the EM ASIC and the design of the FM ASIC.