Snorre Aunet

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

65NM sub-threshold 11T-SRAM for ultra low voltage applications

In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static noise margin (SNM) and the performance. Foundry models for a 65 nm standard CMOS process were used for obtaining reliable simulated results. The circuit was simulated for supply voltages from 0.2 V to 0.35 V verifying the robustness of the proposed circuit for different supply voltages. The simulations show a significant improvement in SNM and a 4X improvement in read speed still maintaining a satisfactory write noise margin compared with the 6T-SRAM cell. The proposed circuit has an area overhead between 22%-28% compared with the 6T-SRAM.

High Speed Ultra Low Voltage CMOS inverter

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.

Ultra low voltage CMOS gates

In this paper we present a CMOS gate which operates on ultra low voltage. We show how to reduce the supply voltage Vdd to Vt without affecting the operational frequency significantly. Moreover, we elaborate on the PDP and EDP improvement compared to footed domino logic CMOS. The paper concludes with measurement from a fabricated chip in a 0.13mum process.

Ultra low power full adder topologies

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (Gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65nm standard models are used for simulations.

Six subthreshold full adder cells characterized in 90 nm CMOS technology

This paper presents a performance analysis and evaluation of six different 1-bit full adder topologies in deep subthreshold operation. The cells are characterized with respect to delay, power consumption, driving capability, power-delay product (PDP), energy-delay product (EDP) and maximum operating frequency. Both traditional CMOS, a specialized low power cell and minority-3 based full adders are simulated and characterized. PDPs of less than 200 aJ are reported, for FA cells operating at frequencies around 2 MHz, for Vdd=200 mV, dissipating less than 100 nW of average power

Low-power subthreshold to above threshold level shifter in 90 nm process

The use of multiple voltage domains in an integrated circuit has been widely utilized with the aim of finding a tradeoff between power saving and performance. Level shifters allow for effective interfacing between voltage domains supplied by different voltage levels. In this paper we present a low power level shifters in the 90nm technology node capable of converting subthreshold voltage signals to above threshold voltage signals. The level shifter makes use of MTCMOS design technique which gives more design flexibility, especially in low power systems. Post layout simulations indicate low power consumption and low energy consumption across process-, mismatch- and temperature variations. Minimum input voltage attainable while maintaining robust operation is found to be around 180mV, at maximum frequency of 1MHz. The level shifter employs an enable/disable feature, allowing for power saving when the level shifter is not in use.

Pseudo Floating-Gate Inverter with Feedback Control

In this paper, the authors present pseudo-floating-gate (PFG) binary and analog inverters with feedback control. The PFG inverter can be used to implement digital, multiple-valued (MV) and analog circuits. The PFG inverter will suppress low frequency components due to a local feedback. PFG circuits can be utilized for low voltage (LV) binary-, multiple valued logic and analog circuits. Typical applications are detection of high frequency components in sensory signals, i.e. airbag sensors. A differential LV amplifier is presented. Simulated data is valid for a CMOS process with at threshold voltage equal to 0.4V. The circuits has been implemented in a 130nm CMOS process

Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS

This paper describes using theory, computer simulations, and laboratory measurements a new class of real-time reconfigurable UV-programmable floating-gate (FGUVMOS) linear threshold elements operating with current levels typically in the pA to /spl mu/A range, in standard double-poly 0.6 /spl mu/m CMOS, providing an ultra low-power potential. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I-O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components compared to previously reported FGUVMOS. 2-MOSFET circuits able to implement CARRY, NOR, NAND, and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. The basic linear threshold element proposed is considered as a potential basic building block in neural networks.

Ultra low power fault tolerant neural inspired CMOS logic

We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ power-delay-product for supply voltages below 100 mV, in a 120 nm process. The power-delay-product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.