H. Schafer

Vertical MOS transistors with 70 nm channel length

Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to ballistic and floating substrate effects. Besides high saturation currents due to very short channel lengths a higher integration density seems to be feasible using this vertical transistor technology.

Oxidation Enhanced Diffusion of Boron in Silicon‐on‐Insulator Substrates

The oxidation enhanced diffusion (OED) of boron and diffusion as well as recombination of interstitials on silicon-on-insulator (SOI) material have been studied in periodically boron-doped silicon. Bonded wafers (BESOI UNIBOND) as well as oxygen-implanted wafers (SIMOX) have been used to consider different interfacial morphologies. Diffusion experiments were performed in the temperature range of 800 to 1050°C and compared with SUPREM-IV simulation results. Parameters like recombination velocity and diffusivity of interstitials have been extracted. Results show for the first time that OED is effectively reduced in SOI material in the near Si/SiO 2 -interface region as well as in the surface region.

Process- and Devicesimulation of Very High Speed Vertical MOS Transistors

Optical lithography does not allow the scaling of MOS transistors down to 100nm dimensions. Thus the channel length of high speed MOS devices must depend on alternative processing steps. In this work layer deposition and etching are analysed with respect to the formation of very short MOS transistors with vertical orientation. Dopant diffusion with very steep gradients are studied in epitaxial layers. Process and device engineering aspects for a vertical MOS transistor at the sidewall of an etched trench are discussed.