Hansoo Kim

High-performance and low-power memory-interface architecture for video processing applications

To improve memory bandwidth and power consumption in video applications, a new memory-interface architecture is proposed. The architecture adopts an array address-translation technique to utilize the fact that video processing algorithms have regular memory-access patterns. Since the translation can minimize the number of overhead cycles needed for row-activations in synchronous DRAM (SDRAM), we can improve the memory bandwidth and energy consumption significantly. The features of SDRAM and memory-access patterns of video processing applications are considered to find a suitable address translation. Compared to the conventional linear translation, experimental results show that the proposed architecture reduces about 89% of row-activations and increases the memory bandwidth by 50%. In addition, the proposed architecture reduces the energy consumption by 30% on the average.

FIR filter synthesis algorithms for minimizing the delay and the number of adders

As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the constant coefficient multiplications required in filters. Although the complexity of multiplier blocks is significantly reduced by using efficient techniques such as decomposing multiplications into simple operations and sharing common subexpressions, previous works have not considered the delay of multiplier blocks which is a critical factor in the design of complex filters. In this paper, we present new algorithms to minimize the complexity of multiplier blocks under the given delay constraints. By analyzing multiplier blocks in view of delay, three delay reduction methods are proposed and combined into previous algorithms. Since the proposed algorithms can generate multiplier blocks that meet the specified delay, a trade-off between delay and hardware complexity is enabled by changing the delay constraints. Experimental results show that the proposed algorithms can reduce the delay of multiplier blocks at the cost of a little increase of complexity.

Multi-thread VLIW processor architecture for HDTV decoding

This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.

Digital signal processor with efficient RGB interpolation and histogram accumulation

We present a new digital signal processor developed for digital camcorder applications. Taking the digital image signal from A/D converter, the signal processor generates luminance and chrominance signals of the image using an efficient RGB interpolation algorithm and histogram accumulation. We propose a low-cost RGB interpolation algorithm that has little image degradation and show the usefulness of histogram accumulation implemented in the signal processor.

A new buffer control strategy for image data compression

In video coding, a rate buffer control strategy is important. The paper introduces a new rate buffer control using a nonlinear relationship between the buffer occupancy and the quantization step size. A piecewise linear relationship is also considered to obtain a better utilization of buffer. The strategy is implemented on H.261 in simulation. In simulations, it was shown that a better SNR ratio can be obtained by the proposed strategy. >

A multi-threading MPEG processor with variable issue modes

MPEG decoding chips have to support multiple features such as video stream decoding, transport stream parsing, multi-standard support, scan line conversion for on-screen display, and audio/video synchronization. Some of these features are computation-intensive, while others are size-intensive. In this paper an embedded processor specialized for the MPEG decoding is proposed to cope with the complicated requirements. The proposed processor can execute up to four operations at a time to handle intensive computation, and can change instruction issue rate according to the required performance in order to save code size which is very important in MPEG applications. In addition, the processor can switch tasks rapidly to keep the number of buffers existing between tasks minimal.

A single-chip MP@HL HDTV decoder with integrated audio decoding and display processing units

A single-chip MP@HL HDTV decoder that integrates all the functions of HDTV such as system parsing, audio decoding, video decoding and display processing is presented. By employing a programmable system parsing unit, the decoder can be applied to not only ATSC receivers but also DVB receivers or DVD players. All 18 ATSC format videos can be decoded and displayed on HD monitors or PC VGA monitors. The decoder also features arbitrary resolution conversion and powerful de-interlacing.

Node sampling technique to speed up probability-based power estimation methods

We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces the number of nodes actually processed. In addition, it is also different from the previous statistical sampling simulation techniques for simulation-based methods in that the previous methods sample the input vectors while our method samples the nodes in the network. The experimental results are very encouraging. The proposed method shows on the average more than 80% and 60% reductions of simulation run time under 20% and 5% error bounds, respectively.