Chung-Wei Ku

A cost-effective architecture for 8/spl times/8 two-dimensional DCT/IDCT using direct method

Among the various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical image and video coding applications, such as high-definition television (HDTV). We develop a novel 8/spl times/8 two-dimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of a complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the proposed architecture is regular and economically allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row-column method with 30% hardware increased.

Power-efficient FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data-flow scheme with modified canonical signed digit (CSD) representation, experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead.

Low power 2D DCT chip design for wireless multimedia terminals

In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.

A low power 2D DCT chip design using direct 2D algorithm

In this paper, a low power 8/spl times/8 2D DCT architecture based on direct 2D approach is proposed. The direct 2D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, a hybrid-architecture adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.

Low power strategy about correlator array for CDMA baseband processor

This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture.

Tree-structure architecture and VLSI implementation for vector quantization algorithms

A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper, The proposed folded-tree architecture is designed by 0.8 /spl mu/m CMOS VLSI technology. The die size is 4.65/spl times/5.21 mm/sup 2/ and estimated clock rate is about 34 MHz, which satisfies most real-time applications. Since it is basically a mean squared error computation circuit, various kinds of VQ algorithms can apply on the proposed architecture.<<ETX>>

A pseudo-object-oriented very low bit-rate video coding system with cache VQ for detail compensation

A pseudo object-oriented video coding system is proposed and implemented. In order to increase the coding efficiency, a cache VQ algorithm is suggested to further compress those areas where motion estimation fails. According to our primary simulation results, the visual quality of long-timed sequences is still acceptable even for bit-rates below 10 kbps. In addition to the high compression ratio for very low bit-rates, content-based applications are also expected since the proposed system utilizes the segmented motion field; furthermore, the occurrences of prediction errors generally locate at emotionally important parts, e.g. eyes and mouth, etc. All the coded components are not only useful for compression but also meaningful for video recognition.

Investigation of a visual telephone prototyping on personal computers

An investigation of a visual telephone prototyping is presented. All the related standards such as system requirements, video codec, and speech codec are introduced. Since the most time-consuming task is video encoding, more details about the H.263 video codec standard are explained. In addition, the strategies for real-time transmission and processing are discussed. From the simulation results, the suggested prototype on personal computers shows the potential on multimedia communication for consumer products.

Building a pseudo object-oriented very low bit-rate video coding system from a modified optical flow motion estimation algorithm

A modified optical flow algorithm (MOFA) is proposed for the development of a very low bit-rate video coding system. Another edge preserving constraint and pyramid approach are suggested to generate an accurate motion field and reduce the possibility of being trapped in a local minimum. Post-processing schemes are also designed to eliminated the problems for special regions. Compared with other motion estimation algorithms, the proposed method gives a more exact estimation in terms of the PSNR and subjective view. The arbitrarily shaped transform of the motion field is then selected to further remove the spatial redundancy. According to some primary simulation results, most of the test sequences are compressed into 16 kbps or lower with excellent picture quality.

The arbitrarily shaped transform of segmented motion field for a pseudo object-oriented very low bit-rate video coding system

The arbitrarily shaped transform (AST) of the segmented motion field generated by modified optical flow algorithm (MOFA) is suggested in this paper. Because the transform kernels are dependent on the shape of the coded region, information about the contours of the objects must be transmitted. To achieve data compression, a coefficient selection function (CSF) is defined for AST coefficients reduction. Since shape information data intensive, a rectangle approximation method is also developed. According to the simulation results, the proposed coding method is efficient and its performance is much better than the traditional block matching algorithm in terms of PSNR and bit-rate. In addition, the proposed algorithms are integrated together to build a very low bit-rate video coding system. From some primary simulations of the system, the proposed method can guarantee 34 dB PSNR for most cases at around 10 kbps; furthermore, the segmentation of objects has potential for object scalability.