Hao-Yi Tsai

A self-aligned airgap interconnect scheme

A new air-gap interconnect scheme with no additional patterning step successfully resolves the issue of unlanded via, and provides good interconnect reliability and improved packaging margin. We demonstrate that the insertion of airgaps in a very low-k dielectric (k=2.5) reduces the RC value of a 0.07um/0.07um comb structure by ∼14%, which is equivalent to an effective dielectric constant about 2.2.

Chip-packaging interaction in Cu/very low-k interconnect

Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.

A Self-Aligned Air Gap Interconnect Process

A self-aligned air gap interconnect structure with sidewall reinforcement is developed. The new structure lowers the capacitance of 0.09um/0.09um (w/s) metal wires by as much as 25%, and exhibits low leakage current. As compared to un-protected air gaps, the structure also greatly improves the electromigration resistance and the misalignment margin for unlanded vias. Furthermore, the sidewall protection layer strengthens the overall mechanical strength and increases the packaging reliability.