Chen-Hua Yu

High-aspect ratio through silicon via (TSV) technology

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

An ultra-thin interposer utilizing 3D TSV technology

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

Production Worthy 3D Interconnect Technology

A three dimensional integrated circuit (3DIC) integration flow, process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity and resulted in good electrical performance. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. By wafer level electrical testing, yielding 20K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated.

A Self-Aligned Air Gap Interconnect Process

A self-aligned air gap interconnect structure with sidewall reinforcement is developed. The new structure lowers the capacitance of 0.09um/0.09um (w/s) metal wires by as much as 25%, and exhibits low leakage current. As compared to un-protected air gaps, the structure also greatly improves the electromigration resistance and the misalignment margin for unlanded vias. Furthermore, the sidewall protection layer strengthens the overall mechanical strength and increases the packaging reliability.