Hariharsudan Sivaramakrishnan Radhakrishnan

Improving the Quality of Epitaxial Foils Produced Using a Porous Silicon-based Layer Transfer Process for High-Efficiency Thin-Film Crystalline Silicon Solar Cells

A porous silicon-based layer transfer process to produce thin (30-50 μm) kerfless epitaxial foils (epifoils) is a promising approach toward high-efficiency solar cells. For high efficiencies, the epifoil must have high minority carrier lifetimes. The epifoil quality depends on the properties of the porous layer since it is the template for epitaxy. It is shown that by reducing the thickness of this layer and/or its porosity in the near-surface region, the near-surface void size is reduced to <;65 nm and in certain cases achieve a 100 nm-thick void-free zone below the surface. Together with better void alignment, this allows for a smoother growth surface with a roughness of <;35 Å and reduced stress in the porous silicon. These improvements translate into significantly diminished epifoil crystal defect densities as low as ~420 defects/cm 2. Although epifoils on very thin porous silicon were not detachable, a significant improvement in the lifetime (diffusion length) of safely detachable n-type epifoils from ~85 (~300 μm) to ~195 μs (~470 μm) at the injection level of 10 15/cm 3 is achieved by tuning the porous silicon template. Lifetimes exceeding ~350 μs have been achieved in the reference lithography-based epifoils, showing the potential for improvement in porous silicon-based epifoils.

High-quality epitaxial foils, obtained by a layer transfer process, for integration in back-contacted solar cells processed on glass

Foil creation by lifting off a thin layer of a high quality silicon substrate is one of the promising substitutes for wafer sawing to create substrates thinner than 100 μm. The porous silicon-based layer transfer process is a well known method to obtain high quality foils. Despite a number of convincing lab-based solar cell show-cases, there is no breakthrough of this technology at (semi)-industrial level, because of the poor yield of processing free standing foils. This paper presents a method to fabricate back contacted solar cells based on epitaxial foils avoiding processes on free-standing foils. First, a porous silicon layer is electrochemically etched, acting as a weak sacrificial layer to detach the foil that is epitaxially grown on top of the porous silicon layer. Characterization of the epitaxial foils shows a good crystalline quality and an effective lifetime around 100 μs. Those results give indications that the obtained foils are well suited for solar cell fabrication. Front-side processing is done while the epitaxial foil is still attached to its parent substrate. A good yield is obtained for epitaxial foils that underwent the front-side processing sequence consisting of wet chemical texturing, FSF formation, passivation and ARC deposition. Afterwards, the front-side of the foil is bonded to a glass carrier and the foil is detached from its parent substrate. Silicone adhesives are used for this permanent bond. The rear-side of the solar cell is processed while bonded to glass. Therefore, only low temperature processes (<;200°C) can be used. So far, the rear-side processing sequence was performed on Float-zone reference wafers as a proof of concept resulting in a confirmed maximum efficiency of 18.4%. The rear-side processing sequence still needs to be applied on epitaxial foils.

Tuning of strain and surface roughness of porous silicon layers for higher-quality seeds for epitaxial growth

Sintered porous silicon is a well-known seed for homo-epitaxy that enables fabricating transferrable monocrystalline foils. The crystalline quality of these foils depends on the surface roughness and the strain of this porous seed, which should both be minimized. In order to provide guidelines for an optimum foil growth, we present a systematic investigation of the impact of the thickness of this seed and of its sintering time prior to epitaxial growth on strain and surface roughness. Strain and surface roughness were monitored in monolayers and double layers with different porosities as a function of seed thickness and of sintering time by high-resolution X-ray diffraction and profilometry, respectively. Unexpectedly, we found that strain in double and monolayers evolves in opposite ways with respect to layer thickness. This suggests that an interaction between layers in multiple stacks is to be considered. We also found that if higher seed thickness and longer annealing time are to be preferred to minimize the strain in double layers, the opposite is required to achieve smoother layers. The impact of these two parameters may be explained by considering the morphological evolution of the pores upon sintering and, in particular, the disappearance of interconnections between the porous seed and the bulk as well as the enlargement of pores near the surface. An optimum epitaxial growth hence calls for a trade-off in seed thickness and annealing time, between minimum-strained layers and rougher surfaces.PACS codes81.40.-z Treatment of materials and its effects on microstructure, nanostructure, and properties; 81.05.Rm Porous materials; granular materials; 82.80.Ej X-ray, Mössbauer and other γ-ray spectroscopic analysis methods

Module-level cell processing of silicon heterojunction interdigitated back-contacted (SHJ-IBC) solar cells with efficiencies above 22%: Towards all-dry processing

Module-level processing of silicon heterojunction interdigitated back-contacted (SHJ-IBC) solar cells while bonded to glass, in the so-called i2-module concept, is discussed. In this approach, a key challenge is the interdigitated patterning of a-Si:H without compromising on the rear-surface passivation. Process adaptations involving more resistant bonding agents and a milder wet etchant enabled bonded cells with the best efficiency of 21.7% and Voc of 734 mV, which are the highest reported for bonded cells processed partially at module level, and which undoubtedly proves the potential of this i2-module concept to reach high Voc and efficiency. Yet another challenge is to make the process flow cost-effective and industrially-relevant, i.e. a litho-free, all-dry process flow, analogous to thin-film PV module fabrication. As a first step, dry etching of a-Si:H was developed to replace wet etching, and was successfully incorporated in a SHJ-IBC process flow to fabricate freestanding cells with the best efficiency of 22.9% and above 20% on thick (190 μm) and thin (56 μm) EVA-bonded silicon.

Dry etch damage in n-type crystalline silicon wafers assessed by deep-level transient spectroscopy and minority carrier lifetime

This paper compares the electrically active damage in dry-etched n-type float-zone silicon, using NF3/Ar or H2-plasma exposure and assessed by deep-level transient spectroscopy (DLTS) and recombination lifetime analysis. It is shown that the NF3/Ar-plasma damage consists of at least four different types of electron traps in the upper half of the band gap, which can be associated with vacancy- and vacancy-impurity-related complexes. In the case of H2-plasma damage, it is believed that the accumulation of point defects results in a gradual disordering of the near-surface layer. These defect levels also act as recombination centers, judged by the fact that they degrade the minority carrier lifetime. It is finally shown that lifetime measurements are more sensitive to the etching-induced damage than DLTS.This paper compares the electrically active damage in dry-etched n-type float-zone silicon, using NF3/Ar or H2-plasma exposure and assessed by deep-level transient spectroscopy (DLTS) and recombination lifetime analysis. It is shown that the NF3/Ar-plasma damage consists of at least four different types of electron traps in the upper half of the band gap, which can be associated with vacancy- and vacancy-impurity-related complexes. In the case of H2-plasma damage, it is believed that the accumulation of point defects results in a gradual disordering of the near-surface layer. These defect levels also act as recombination centers, judged by the fact that they degrade the minority carrier lifetime. It is finally shown that lifetime measurements are more sensitive to the etching-induced damage than DLTS.

2D periodic photonic nanostructures integrated in 40 _x0019_

Two-dimensional (2D) periodic photonic nanostructures are fabricated by nanoimprint lithography (NIL) and dry plasma (Dry-NIL) etching on 40 μm thick epitaxially-grown crystalline silicon (c-Si) foils, resulting in nanostructures with a parabolic profile. These nanostructures are integrated in a 40 μm thick double side contacted c-Si/aSi:H heterojunction solar cell architecture. The front side is processed when the foil is attached to the parent substrate while the back side is processed when the foil is bonded to the glass carrier. Although the efficiency of the nanopatterned cell was lower compared to the random pyramid textured cells it had a better absorption and spectral response for long wavelengths, highlighting a better light trapping behavior.

lm thin crystalline silicon solar cells

In epitaxial silicon solar cells grown on low-cost substrates, an embedded porous silicon layer is used to block metal diffusion from the substrate into the epitaxial active layer. The gettering efficiency of porous silicon can be enhanced by reducing the pore radius. In the size range (27.2 nm-39.8 nm) investigated, the additional curvature of the 27.2 nm void leads to >200 meV improvement in the binding energy for both copper and nickel, enhancing the gettering efficiency by >10 times. This is due to the existence of specific binding sites which allows greater dangling bond passivation in smaller voids.